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SystemVerilog to Verilog conversion
31 Commits 1 Branch 14 Tags 3.4 MiB
Haskell 48.1%
SystemVerilog 26.2%
Verilog 16.4%
Yacc 6.4%
Shell 2.5%
Other 0.3%
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Zachary Snow f11f1efea1 address warnings in Preprocess.hs 2019-02-18 02:28:44 -05:00
Convert always construct conversion; more modular conversion approach 2019-02-18 01:38:16 -05:00
Language address warnings in Preprocess.hs 2019-02-18 02:28:44 -05:00
.gitignore switch to using stack 2019-02-11 23:48:49 -05:00
Convert.hs always construct conversion; more modular conversion approach 2019-02-18 01:38:16 -05:00
LICENSE updated LICENSE to reflect fork 2019-02-08 16:51:20 -05:00
Makefile switch to using stack 2019-02-11 23:48:49 -05:00
Setup.hs Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00
stack.yaml switch to using stack 2019-02-11 23:48:49 -05:00
sv2v.cabal always construct conversion; more modular conversion approach 2019-02-18 01:38:16 -05:00
sv2v.hs added logic to module items; toying with initial Conversion 2019-02-17 23:39:01 -05:00