mirror of https://github.com/zachjs/sv2v.git
32 lines
561 B
Haskell
32 lines
561 B
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- SystemVerilog to Verilog conversion
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-}
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module Convert (convert) where
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import Language.SystemVerilog.AST
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import qualified Convert.AlwaysKW
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import qualified Convert.Logic
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type Phase = [Module] -> [Module]
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phases :: [Phase]
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phases =
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[ Convert.AlwaysKW.convert
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, Convert.Logic.convert
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]
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run :: Phase
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run = foldr (.) id phases
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convert :: Phase
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convert modules =
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let modules' = run modules
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in
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if modules == modules'
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then modules
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else convert modules'
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