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sv2v
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SystemVerilog to Verilog conversion
38 Commits 1 Branch 14 Tags 3.4 MiB
Haskell 48.1%
SystemVerilog 26.2%
Verilog 16.4%
Yacc 6.4%
Shell 2.5%
Other 0.3%
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Zachary Snow b81341c0ac support for casex and casez, and their conversions 2019-02-23 15:10:25 -05:00
Convert support for casex and casez, and their conversions 2019-02-23 15:10:25 -05:00
Language support for casex and casez, and their conversions 2019-02-23 15:10:25 -05:00
.gitignore switch to using stack 2019-02-11 23:48:49 -05:00
Convert.hs support for casex and casez, and their conversions 2019-02-23 15:10:25 -05:00
LICENSE updated LICENSE to reflect fork 2019-02-08 16:51:20 -05:00
Makefile switch to using stack 2019-02-11 23:48:49 -05:00
Setup.hs Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00
stack.yaml switch to using stack 2019-02-11 23:48:49 -05:00
sv2v.cabal support for casex and casez, and their conversions 2019-02-23 15:10:25 -05:00
sv2v.hs added logic to module items; toying with initial Conversion 2019-02-17 23:39:01 -05:00