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SystemVerilog to Verilog conversion
3 Commits 1 Branch 14 Tags 3.4 MiB
Haskell 48.1%
SystemVerilog 26.2%
Verilog 16.4%
Yacc 6.4%
Shell 2.5%
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Zachary Snow b46009af53 Refactor project setup for our purposes 2019-02-08 00:19:39 -05:00
Data Fix compiliation; trailing whitespace; added .gitignore 2019-02-07 23:58:34 -05:00
Language Refactor project setup for our purposes 2019-02-08 00:19:39 -05:00
.gitignore Fix compiliation; trailing whitespace; added .gitignore 2019-02-07 23:58:34 -05:00
LICENSE Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00
Setup.hs Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00
sv2v.cabal Refactor project setup for our purposes 2019-02-08 00:19:39 -05:00
sv2v.hs Refactor project setup for our purposes 2019-02-08 00:19:39 -05:00