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luke/sv2v
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mirror of https://github.com/zachjs/sv2v.git synced 2026-09-03 16:39:06 +02:00
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35 Commits 2 Branches 14 Tags
546657d2c366002f4cb4d6eefc8a6c2e2b1b5390
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Zachary Snow 546657d2c3 added (very hacky) PackedArrayFlatten conversion; convert logics in generate
2019-02-21 20:12:34 -05:00
Convert
added (very hacky) PackedArrayFlatten conversion; convert logics in generate
2019-02-21 20:12:34 -05:00
Language
added (very hacky) PackedArrayFlatten conversion; convert logics in generate
2019-02-21 20:12:34 -05:00
.gitignore
switch to using stack
2019-02-11 23:48:49 -05:00
Convert.hs
added (very hacky) PackedArrayFlatten conversion; convert logics in generate
2019-02-21 20:12:34 -05:00
LICENSE
updated LICENSE to reflect fork
2019-02-08 16:51:20 -05:00
Makefile
switch to using stack
2019-02-11 23:48:49 -05:00
Setup.hs
Initial commit: fork of https://github.com/tomahawkins/verilog
2019-02-07 23:49:12 -05:00
stack.yaml
switch to using stack
2019-02-11 23:48:49 -05:00
sv2v.cabal
added (very hacky) PackedArrayFlatten conversion; convert logics in generate
2019-02-21 20:12:34 -05:00
sv2v.hs
added logic to module items; toying with initial Conversion
2019-02-17 23:39:01 -05:00
S
Description
SystemVerilog to Verilog conversion
conversionsystemverilogverilogyosys
BSD-3-Clause
3.3 MiB
Languages
Haskell 48.1%
SystemVerilog 26.3%
Verilog 16.4%
Yacc 6.4%
Shell 2.4%
Other 0.3%
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