SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

Zachary Snow 50996f0d67 support for integers with arrays or assignments; more complete and standardized support for multiple reg/integer declarations in procedural blocks		2019-02-11 14:46:09 -05:00
Data	Basic build setup!	2019-02-08 01:09:33 -05:00
Language	support for integers with arrays or assignments; more complete and standardized support for multiple reg/integer declarations in procedural blocks	2019-02-11 14:46:09 -05:00
.gitignore	updated build procedure	2019-02-08 16:51:32 -05:00
LICENSE	updated LICENSE to reflect fork	2019-02-08 16:51:20 -05:00
Makefile	updated build procedure	2019-02-08 16:51:32 -05:00
Setup.hs	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
sv2v.cabal	updated build procedure	2019-02-08 16:51:32 -05:00
sv2v.hs	support for reduction ops, non-named/non-identifier module instantiation arguments, always @*	2019-02-10 17:47:11 -05:00