Zachary Snow 27147c5489 some tweaks to output formatting

2019-02-24 03:19:02 -05:00

Convert

huge pass at revamping AST to be more general, easy to work with

2019-02-24 03:06:40 -05:00

Language

some tweaks to output formatting

2019-02-24 03:19:02 -05:00

.gitignore

switch to using stack

2019-02-11 23:48:49 -05:00

Convert.hs

support for casex and casez, and their conversions

2019-02-23 15:10:25 -05:00

LICENSE

updated LICENSE to reflect fork

2019-02-08 16:51:20 -05:00

Makefile

switch to using stack

2019-02-11 23:48:49 -05:00

Setup.hs

Initial commit: fork of https://github.com/tomahawkins/verilog

2019-02-07 23:49:12 -05:00

stack.yaml

switch to using stack

2019-02-11 23:48:49 -05:00

sv2v.cabal

support for casex and casez, and their conversions

2019-02-23 15:10:25 -05:00

sv2v.hs

added logic to module items; toying with initial Conversion

2019-02-17 23:39:01 -05:00

S

Description

SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

BSD-3-Clause

3.3 MiB

Languages

Haskell 48.1%

SystemVerilog 26.3%

Verilog 16.4%

Yacc 6.4%

Shell 2.4%

Other 0.3%