mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 09:28:12 +02:00
5 lines
143 B
Verilog
5 lines
143 B
Verilog
module top;
|
|
reg [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
|
|
initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
|
|
endmodule
|