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15 lines
291 B
Verilog
15 lines
291 B
Verilog
module top;
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localparam [2:0] AccessAck = 3'd0;
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wire [2:0] test;
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reg start;
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always @(*) begin
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if (start);
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case (test)
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AccessAck: $display("Ack");
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default : $display("default");
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endcase
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end
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initial start = 0;
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endmodule
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