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11 lines
171 B
Systemverilog
11 lines
171 B
Systemverilog
module top;
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reg x, y;
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initial begin
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$monitor($time, x, y);
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#1 x = 0;
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#1 x = 1;
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#0.75 y = 0;
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#0.75 y = 1;
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end
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endmodule
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