support bare delay controls with real number delays

CHANGELOG.md

@@ -16,6 +16,7 @@
 * Tolerate escaped vendor block comments in macro bodies
 * Support deferred immediate assertion statements
 * Apply implicit port directions to tasks and functions
+* Support bare delay controls with real number delays
 
 ## v0.0.8
 

src/Language/SystemVerilog/Parser/Parse.y

@@ -1162,6 +1162,7 @@ DelayOrEvent :: { Timing }
   | EventControl { Event $1 }
 DelayControl :: { Expr }
   : "#" Number { Number $2 }
+  | "#" Real   { Real   $2 }
   | "#" Time   { Time   $2 }
   | "#" "(" Expr ")"  { $3 }
   | "#" "(" Expr ":" Expr ":" Expr ")" { MinTypMax $3 $5 $7 }

test/basic/delay_real.sv

@@ -0,0 +1,10 @@
+module top;
+    reg x, y;
+    initial begin
+        $monitor($time, x, y);
+        #1 x = 0;
+        #1 x = 1;
+        #0.75 y = 0;
+        #0.75 y = 1;
+    end
+endmodule