7 Commits

Author	SHA1	Message	Date
Zachary Snow	14ba5dae6d	support for reduction ops, non-named/non-identifier module instantiation arguments, always @*	2019-02-10 17:47:11 -05:00
Zachary Snow	5b336439fb	cleanup of port decl parsing	2019-02-09 18:35:15 -05:00
Zachary Snow	ebd7ae67b1	hacky, preliminary support for port declarations in module header	2019-02-09 17:35:31 -05:00
Zachary Snow	8bd58e961f	Basic build setup!	2019-02-08 01:09:33 -05:00
Zachary Snow	b46009af53	Refactor project setup for our purposes	2019-02-08 00:19:39 -05:00
Zachary Snow	bfafea5dd8	Fix compiliation; trailing whitespace; added .gitignore	2019-02-07 23:58:34 -05:00
Zachary Snow	363ca80af2	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00