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support implied port directions

This commit is contained in:
Zachary Snow 2020-02-08 21:14:03 -05:00
parent 4b3b09d2db
commit fc9999aeea
1 changed files with 13 additions and 1 deletions
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14
src/Language/SystemVerilog/Parser/ParseDecl.hs
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@ -105,10 +105,22 @@ parseDTsAsPortDecls pieces =
length pieces == length commaIdxs + length identIdxs
simpleIdents = map extractIdent $ filter isIdent pieces
declarations = parseDTsAsDecls pieces
declarations = propagateDirections Input $ parseDTsAsDecls pieces
extractIdent = \(DTIdent _ x) -> x
propagateDirections :: Direction -> [Decl] -> [Decl]
propagateDirections dir (decl @ (Variable _ InterfaceT{} _ _ _) : decls) =
decl : propagateDirections dir decls
propagateDirections lastDir (Variable currDir t x a me : decls) =
decl : propagateDirections dir decls
where
decl = Variable dir t x a me
dir = if currDir == Local then lastDir else currDir
propagateDirections dir (decl : decls) =
decl : propagateDirections dir decls
propagateDirections _ [] = []
portNames :: [Decl] -> [Identifier]
portNames items = mapMaybe portName items
portName :: Decl -> Maybe Identifier