allow extraneous semicolons in generate blocks

src/Language/SystemVerilog/Parser/Parse.y

@@ -1227,6 +1227,7 @@ GenItemOrNull :: { GenItem }
 
 GenItems :: { [GenItem] }
   : {- empty -}      { [] }
+  | GenItems ";"     { $1 }
   | GenItems GenItem { $1 ++ [$2] }
 
 GenItem :: { GenItem }

test/basic/for_decl.sv

@@ -66,6 +66,7 @@ module top;
 
     logic [0:31] c;
     generate
+        ;
         for (genvar n = 0; n < 32; n = n + 1)
             assign c[n] = n & 1;
     endgenerate