added pass-through support for strings

src/Convert/Struct.hs

@@ -170,7 +170,9 @@ traverseDeclM structs origDecl = do
     case origDecl of
         Variable d t x a me -> do
             let (tf, rs) = typeRanges t
-            modify $ Map.insert x (tf $ a ++ rs)
+            if isRangeable t
+                then modify $ Map.insert x (tf $ a ++ rs)
+                else return ()
             case me of
                 Nothing -> return origDecl
                 Just e -> do
@@ -188,6 +190,10 @@ traverseDeclM structs origDecl = do
             types <- get
             let (LHSIdent _, e') = convertAsgn structs types (LHSIdent x, e)
             return e'
+        isRangeable :: Type -> Bool
+        isRangeable (IntegerAtom _ _) = False
+        isRangeable (NonInteger  _  ) = False
+        isRangeable _ = True
 
 -- produces a function which packs the components of a struct literal
 packerFn :: TypeFunc -> ModuleItem

src/Language/SystemVerilog/AST/Type.hs

@@ -146,6 +146,7 @@ data NonIntegerType
     = TShortreal
     | TReal
     | TRealtime
+    | TString
     deriving (Eq, Ord)
 
 instance Show NetType where
@@ -176,6 +177,7 @@ instance Show NonIntegerType where
     show TShortreal = "shortreal"
     show TReal      = "real"
     show TRealtime  = "realtime"
+    show TString    = "string"
 
 data Packing
     = Unpacked

src/Language/SystemVerilog/Parser/Parse.y

@@ -485,6 +485,7 @@ NonIntegerType :: { NonIntegerType }
   : "shortreal" { TShortreal }
   | "real"      { TReal      }
   | "realtime"  { TRealtime  }
+  | "string"    { TString    }
 
 EnumItems :: { [(Identifier, Maybe Expr)] }
   : VariablePortIdentifiers { $1 }