From f4181aba768bc87f237875b857537c18f18ca3c0 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 24 Sep 2019 21:48:10 -0400
Subject: [PATCH] added pass-through support for strings

---
 src/Convert/Struct.hs                     | 8 +++++++-
 src/Language/SystemVerilog/AST/Type.hs    | 2 ++
 src/Language/SystemVerilog/Parser/Parse.y | 1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/Convert/Struct.hs b/src/Convert/Struct.hs
index 1583a41..2d40746 100644
--- a/src/Convert/Struct.hs
+++ b/src/Convert/Struct.hs
@@ -170,7 +170,9 @@ traverseDeclM structs origDecl = do
     case origDecl of
         Variable d t x a me -> do
             let (tf, rs) = typeRanges t
-            modify $ Map.insert x (tf $ a ++ rs)
+            if isRangeable t
+                then modify $ Map.insert x (tf $ a ++ rs)
+                else return ()
             case me of
                 Nothing -> return origDecl
                 Just e -> do
@@ -188,6 +190,10 @@ traverseDeclM structs origDecl = do
             types <- get
             let (LHSIdent _, e') = convertAsgn structs types (LHSIdent x, e)
             return e'
+        isRangeable :: Type -> Bool
+        isRangeable (IntegerAtom _ _) = False
+        isRangeable (NonInteger  _  ) = False
+        isRangeable _ = True
 
 -- produces a function which packs the components of a struct literal
 packerFn :: TypeFunc -> ModuleItem
diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs
index 57705eb..5f52d90 100644
--- a/src/Language/SystemVerilog/AST/Type.hs
+++ b/src/Language/SystemVerilog/AST/Type.hs
@@ -146,6 +146,7 @@ data NonIntegerType
     = TShortreal
     | TReal
     | TRealtime
+    | TString
     deriving (Eq, Ord)
 
 instance Show NetType where
@@ -176,6 +177,7 @@ instance Show NonIntegerType where
     show TShortreal = "shortreal"
     show TReal      = "real"
     show TRealtime  = "realtime"
+    show TString    = "string"
 
 data Packing
     = Unpacked
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 87dee35..9bf0117 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -485,6 +485,7 @@ NonIntegerType :: { NonIntegerType }
   : "shortreal" { TShortreal }
   | "real"      { TReal      }
   | "realtime"  { TRealtime  }
+  | "string"    { TString    }
 
 EnumItems :: { [(Identifier, Maybe Expr)] }
   : VariablePortIdentifiers { $1 }