improved portability of logic conversion

- indirect converted reg continuous assignments through wires
- fix typeof for implicitly typed ports
- fix typeof for sized implicitly typed params

test/basic/logic_cond.sv

@@ -1,9 +1,10 @@
 module Example(inp, out);
     parameter ENABLED = 1;
+    localparam [0:0] DEFAULT = 1'b0;
     input logic inp;
     output logic out;
     if (ENABLED)
         always_comb out = inp;
     else
-        assign out = '0;
+        assign out = DEFAULT;
 endmodule

test/basic/logic_cond.v

@@ -1,11 +1,12 @@
 module Example(inp, out);
     parameter ENABLED = 1;
+    localparam [0:0] DEFAULT = 1'b0;
     input wire inp;
     output reg out;
     generate
         if (ENABLED)
             always @* out = inp;
         else
-            initial out = 0;
+            initial out = DEFAULT;
     endgenerate
 endmodule

test/basic/typeof.sv

@@ -77,12 +77,16 @@ module top;
 
     localparam X = 5'b10110;
     localparam Y = X + 6'b00001;
+    localparam [7:0] Z = 234;
     initial begin
         type(X) tX = X;
         type(Y) tY = Y;
+        type(Z) tZ = Z;
         $display("%b %d %d %d", X, X, $left(X), $right(X));
         $display("%b %d %d %d", Y, Y, $left(Y), $right(Y));
+        $display("%b %d %d %d", Z, Z, $left(Z), $right(Z));
         $display("%b %d %d %d", tX, tX, $left(tX), $right(tX));
         $display("%b %d %d %d", tY, tY, $left(tY), $right(tY));
+        $display("%b %d %d %d", tZ, tZ, $left(tZ), $right(tZ));
     end
 endmodule

test/basic/typeof.v

@@ -94,14 +94,19 @@ module top;
 
     localparam X = 5'b10110;
     localparam Y = X + 6'b00001;
+    localparam [7:0] Z = 234;
     initial begin : block5
         reg [4:0] tX;
         reg [5:0] tY;
+        reg [7:0] tZ;
         tX = X;
         tY = Y;
+        tZ = Z;
         $display("%b %d %d %d", X, X, 4, 0);
         $display("%b %d %d %d", Y, Y, 5, 0);
+        $display("%b %d %d %d", Z, Z, 7, 0);
         $display("%b %d %d %d", tX, tX, 4, 0);
         $display("%b %d %d %d", tY, tY, 5, 0);
+        $display("%b %d %d %d", tZ, tZ, 7, 0);
     end
 endmodule

test/basic/typeof_port.sv

@@ -0,0 +1,7 @@
+module Example(inp, out);
+    input inp;
+    output out;
+    type(inp) data;
+    assign data = ~inp;
+    assign out = data;
+endmodule

test/basic/typeof_port.v

@@ -0,0 +1,7 @@
+module Example(inp, out);
+    input inp;
+    output out;
+    wire data;
+    assign data = ~inp;
+    assign out = data;
+endmodule

test/basic/typeof_port_tb.v

@@ -0,0 +1,8 @@
+module top;
+    reg inp;
+    wire out;
+    Example e(inp, out);
+    initial begin
+        $monitor("%0d %b %b", $time, inp, out);
+    end
+endmodule