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preserve generate else branch association in codegen

This commit is contained in:
Zachary Snow 2021-01-25 12:29:34 -05:00
parent e4adf6a74c
commit 5f0dc6be0c
2 changed files with 77 additions and 1 deletions
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16
src/Language/SystemVerilog/AST/GenItem.hs
View File

@ -38,7 +38,7 @@ instance Show GenItem where
printf "case (%s)\n%s\nendcase" (show e) bodyStr
where bodyStr = indent $ unlines' $ map showGenCase cs
show (GenIf e a GenNull) = printf "if (%s) %s" (show e) (show a)
show (GenIf e a b ) = printf "if (%s) %s\nelse %s" (show e) (show a) (show b)
show (GenIf e a b ) = printf "if (%s) %s\nelse %s" (show e) (showBlockedBranch a) (show b)
show (GenFor (x1, e1) c (x2, o2, e2) s) =
printf "for (%s = %s; %s; %s %s %s) %s"
x1 (show e1)
@ -48,6 +48,20 @@ instance Show GenItem where
show (GenNull) = ";"
show (GenModuleItem item) = show item
showBlockedBranch :: GenItem -> String
showBlockedBranch genItem =
show $
if isControl genItem
then GenBlock "" [genItem]
else genItem
where
isControl :: GenItem -> Bool
isControl GenIf{} = True
isControl GenFor{} = True
isControl GenCase{} = True
isControl GenModuleItem{} = True
isControl _ = False
type GenCase = ([Expr], GenItem)
showGenCase :: GenCase -> String

62
test/basic/generate_else_branch.sv Normal file
View File

@ -0,0 +1,62 @@
module Example;
parameter X = 1;
parameter Y = 1;
parameter Z = 1;
initial $display("X=%0d Y=%0d Z=%0d Example", X, Y, Z);
generate
if (X) begin
if (Y) begin
if (Z) begin
initial $display("X=%0d Y=%0d Z=%0d A", X, Y, Z);
end
end
else begin
initial $display("X=%0d Y=%0d Z=%0d B", X, Y, Z);
end
end
initial
if (X) begin
if (Y) begin
if (Z) begin
$display("X=%0d Y=%0d Z=%0d C", X, Y, Z);
end
end
else begin
$display("X=%0d Y=%0d Z=%0d D", X, Y, Z);
end
end
if (X) begin
initial
if (Y) begin
if (Z) begin
$display("X=%0d Y=%0d Z=%0d E", X, Y, Z);
end
end
else begin
$display("X=%0d Y=%0d Z=%0d F", X, Y, Z);
end
end
if (X) begin
if (Y) begin
initial
if (Z) begin
$display("X=%0d Y=%0d Z=%0d G", X, Y, Z);
end
end
else begin
initial $display("X=%0d Y=%0d Z=%0d H", X, Y, Z);
end
end
endgenerate
endmodule
module top;
Example #(0, 0, 0) e000();
Example #(0, 0, 1) e001();
Example #(0, 1, 0) e010();
Example #(0, 1, 1) e011();
Example #(1, 0, 0) e100();
Example #(1, 0, 1) e101();
Example #(1, 1, 0) e110();
Example #(1, 1, 1) e111();
endmodule