From b22cd210a4f2014ec115f9f27bc97f014f43ea8a Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 25 Jan 2021 19:23:54 -0500 Subject: [PATCH] improved portability of logic conversion - indirect converted reg continuous assignments through wires - fix typeof for implicitly typed ports - fix typeof for sized implicitly typed params --- src/Convert/Logic.hs | 24 ++++++++++-------------- src/Convert/TypeOf.hs | 9 ++++++--- test/basic/logic_cond.sv | 3 ++- test/basic/logic_cond.v | 3 ++- test/basic/typeof.sv | 4 ++++ test/basic/typeof.v | 5 +++++ test/basic/typeof_port.sv | 7 +++++++ test/basic/typeof_port.v | 7 +++++++ test/basic/typeof_port_tb.v | 8 ++++++++ 9 files changed, 51 insertions(+), 19 deletions(-) create mode 100644 test/basic/typeof_port.sv create mode 100644 test/basic/typeof_port.v create mode 100644 test/basic/typeof_port_tb.v diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs index 647984b..3cc71ec 100644 --- a/src/Convert/Logic.hs +++ b/src/Convert/Logic.hs @@ -106,21 +106,17 @@ traverseModuleItem ports scopes = fixModuleItem :: ModuleItem -> ModuleItem -- rewrite bad continuous assignments to use procedural assignments fixModuleItem (Assign AssignOptionNone lhs expr) = - if not (isReg lhs) then - Assign AssignOptionNone lhs expr - else if isConstant expr then - Initial $ Asgn AsgnOpEq Nothing lhs expr - else - AlwaysC AlwaysComb $ Asgn AsgnOpEq Nothing lhs expr + if not (isReg lhs) + then Assign AssignOptionNone lhs expr + else + Generate $ map GenModuleItem + [ MIPackageItem (Decl (Variable Local t x [] Nil)) + , Assign AssignOptionNone (LHSIdent x) expr + , AlwaysC AlwaysComb $ Asgn AsgnOpEq Nothing lhs (Ident x) + ] where - -- only handles expressions which are trivially constant for now - isConstant :: Expr -> Bool - isConstant Number{} = True - isConstant (Repeat _ es) = all isConstant es - isConstant (Concat es) = all isConstant es - isConstant (BinOp _ e1 e2) = isConstant e1 && isConstant e2 - isConstant (UniOp _ e) = isConstant e - isConstant _ = False + t = TypeOf expr + x = "sv2v_tmp_" ++ shortHash (lhs, expr) -- rewrite port bindings to use temporary nets where necessary fixModuleItem (Instance moduleName params instanceName rs bindings) = if null newItems diff --git a/src/Convert/TypeOf.hs b/src/Convert/TypeOf.hs index 6367cb9..099bf8c 100644 --- a/src/Convert/TypeOf.hs +++ b/src/Convert/TypeOf.hs @@ -37,11 +37,11 @@ traverseDeclM decl = do item <- traverseModuleItemM (MIPackageItem $ Decl decl) let MIPackageItem (Decl decl') = item case decl' of - Variable Local (Implicit sg rs) ident [] Nil -> do + Variable _ (Implicit sg rs) ident a _ -> -- implicit types, which are commonly found in function return -- types, are recast as logics to avoid outputting bare ranges - insertElem ident $ IntegerVector TLogic sg rs - return decl' + insertElem ident t' >> return decl' + where t' = injectRanges (IntegerVector TLogic sg rs) a Variable d t ident a e -> do let t' = injectRanges t a insertElem ident t' @@ -52,6 +52,9 @@ traverseDeclM decl = do insertElem ident UnknownType >> return decl' Param _ UnknownType ident e -> typeof e >>= insertElem ident >> return decl' + Param _ (Implicit sg rs) ident _ -> + insertElem ident t' >> return decl' + where t' = IntegerVector TLogic sg rs Param _ t ident _ -> insertElem ident t >> return decl' ParamType{} -> return decl' diff --git a/test/basic/logic_cond.sv b/test/basic/logic_cond.sv index 52bc3ef..116b413 100644 --- a/test/basic/logic_cond.sv +++ b/test/basic/logic_cond.sv @@ -1,9 +1,10 @@ module Example(inp, out); parameter ENABLED = 1; + localparam [0:0] DEFAULT = 1'b0; input logic inp; output logic out; if (ENABLED) always_comb out = inp; else - assign out = '0; + assign out = DEFAULT; endmodule diff --git a/test/basic/logic_cond.v b/test/basic/logic_cond.v index 26b48fa..449e494 100644 --- a/test/basic/logic_cond.v +++ b/test/basic/logic_cond.v @@ -1,11 +1,12 @@ module Example(inp, out); parameter ENABLED = 1; + localparam [0:0] DEFAULT = 1'b0; input wire inp; output reg out; generate if (ENABLED) always @* out = inp; else - initial out = 0; + initial out = DEFAULT; endgenerate endmodule diff --git a/test/basic/typeof.sv b/test/basic/typeof.sv index 4bc267d..0ecbf65 100644 --- a/test/basic/typeof.sv +++ b/test/basic/typeof.sv @@ -77,12 +77,16 @@ module top; localparam X = 5'b10110; localparam Y = X + 6'b00001; + localparam [7:0] Z = 234; initial begin type(X) tX = X; type(Y) tY = Y; + type(Z) tZ = Z; $display("%b %d %d %d", X, X, $left(X), $right(X)); $display("%b %d %d %d", Y, Y, $left(Y), $right(Y)); + $display("%b %d %d %d", Z, Z, $left(Z), $right(Z)); $display("%b %d %d %d", tX, tX, $left(tX), $right(tX)); $display("%b %d %d %d", tY, tY, $left(tY), $right(tY)); + $display("%b %d %d %d", tZ, tZ, $left(tZ), $right(tZ)); end endmodule diff --git a/test/basic/typeof.v b/test/basic/typeof.v index b5cea6e..8f0afca 100644 --- a/test/basic/typeof.v +++ b/test/basic/typeof.v @@ -94,14 +94,19 @@ module top; localparam X = 5'b10110; localparam Y = X + 6'b00001; + localparam [7:0] Z = 234; initial begin : block5 reg [4:0] tX; reg [5:0] tY; + reg [7:0] tZ; tX = X; tY = Y; + tZ = Z; $display("%b %d %d %d", X, X, 4, 0); $display("%b %d %d %d", Y, Y, 5, 0); + $display("%b %d %d %d", Z, Z, 7, 0); $display("%b %d %d %d", tX, tX, 4, 0); $display("%b %d %d %d", tY, tY, 5, 0); + $display("%b %d %d %d", tZ, tZ, 7, 0); end endmodule diff --git a/test/basic/typeof_port.sv b/test/basic/typeof_port.sv new file mode 100644 index 0000000..9edf853 --- /dev/null +++ b/test/basic/typeof_port.sv @@ -0,0 +1,7 @@ +module Example(inp, out); + input inp; + output out; + type(inp) data; + assign data = ~inp; + assign out = data; +endmodule diff --git a/test/basic/typeof_port.v b/test/basic/typeof_port.v new file mode 100644 index 0000000..72ea268 --- /dev/null +++ b/test/basic/typeof_port.v @@ -0,0 +1,7 @@ +module Example(inp, out); + input inp; + output out; + wire data; + assign data = ~inp; + assign out = data; +endmodule diff --git a/test/basic/typeof_port_tb.v b/test/basic/typeof_port_tb.v new file mode 100644 index 0000000..9536dbf --- /dev/null +++ b/test/basic/typeof_port_tb.v @@ -0,0 +1,8 @@ +module top; + reg inp; + wire out; + Example e(inp, out); + initial begin + $monitor("%0d %b %b", $time, inp, out); + end +endmodule