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support for functions with no block decls; fix parse of block reg decls

This commit is contained in:
Zachary Snow 2019-02-17 02:59:41 -05:00
parent 57630b77bd
commit 738c2b9efc
1 changed files with 5 additions and 4 deletions
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9
Language/SystemVerilog/Parser/Parse.y
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@ -228,6 +228,7 @@ ModuleItem :: { [ModuleItem] }
FunctionItems :: { [(Bool, BlockItemDeclaration)] }
: "(" FunctionPortList ";" BlockItemDeclarations { (map ((,) True) $2) ++ (map ((,) False) $4) }
| "(" FunctionPortList ";" { (map ((,) True) $2) }
| ";" FunctionItemDeclarations { $2 }
FunctionPortList :: { [BlockItemDeclaration] }
: FunctionInputDeclaration(")") { $1 }
@ -339,10 +340,10 @@ BlockItemDeclarations :: { [BlockItemDeclaration] }
| BlockItemDeclarations BlockItemDeclaration { $1 ++ $2 }
BlockItemDeclaration :: { [BlockItemDeclaration] }
: "reg" opt(Range) BlockVariableIdentifiers { map (uncurry $ BIDReg $2) $3 }
| ParameterDeclaration { map BIDParameter $1 }
| LocalparamDeclaration { map BIDLocalparam $1 }
| IntegerDeclaration { map BIDIntegerV $1 }
: "reg" opt(Range) BlockVariableIdentifiers ";" { map (uncurry $ BIDReg $2) $3 }
| ParameterDeclaration { map BIDParameter $1 }
| LocalparamDeclaration { map BIDLocalparam $1 }
| IntegerDeclaration { map BIDIntegerV $1 }
BlockVariableIdentifiers :: { [(Identifier, [Range])] }
: BlockVariableType { [$1] }
| BlockVariableIdentifiers "," BlockVariableType { $1 ++ [$3] }