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support for begin_keywords directive
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Zachary Snow
parent
3d3359d35a
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- To implement the `begin_keywords` directive, this module defines which IEEE
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- 1800-2017 keywords are not keywords in preceding specifications.
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-}
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module Language.SystemVerilog.Parser.Keywords
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( specMap
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) where
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import qualified Data.Map.Strict as Map
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import qualified Data.Set as Set
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import Language.SystemVerilog.Parser.Tokens
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newKeywords :: [(String, [TokenName])]
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newKeywords = [
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("1364-1995", [KW_always, KW_and, KW_assign, KW_begin, KW_buf, KW_bufif0,
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KW_bufif1, KW_case, KW_casex, KW_casez, KW_cmos, KW_deassign, KW_default,
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KW_defparam, KW_disable, KW_edge, KW_else, KW_end, KW_endcase,
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KW_endfunction, KW_endmodule, KW_endprimitive, KW_endspecify, KW_endtable,
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KW_endtask, KW_event, KW_for, KW_force, KW_forever, KW_fork, KW_function,
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KW_highz0, KW_highz1, KW_if, KW_ifnone, KW_initial, KW_inout, KW_input,
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KW_integer, KW_join, KW_large, KW_macromodule, KW_medium, KW_module,
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KW_nand, KW_negedge, KW_nmos, KW_nor, KW_not, KW_notif0, KW_notif1, KW_or,
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KW_output, KW_parameter, KW_pmos, KW_posedge, KW_primitive, KW_pull0,
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KW_pull1, KW_pulldown, KW_pullup, KW_rcmos, KW_real, KW_realtime, KW_reg,
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KW_release, KW_repeat, KW_rnmos, KW_rpmos, KW_rtran, KW_rtranif0,
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KW_rtranif1, KW_scalared, KW_small, KW_specify, KW_specparam, KW_strong0,
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KW_strong1, KW_supply0, KW_supply1, KW_table, KW_task, KW_time, KW_tran,
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KW_tranif0, KW_tranif1, KW_tri, KW_tri0, KW_tri1, KW_triand, KW_trior,
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KW_trireg, KW_vectored, KW_wait, KW_wand, KW_weak0, KW_weak1, KW_while,
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KW_wire, KW_wor, KW_xnor, KW_xor]),
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("1364-2001-noconfig", [KW_cell, KW_config, KW_design, KW_endconfig,
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KW_incdir, KW_include, KW_instance, KW_liblist, KW_library, KW_use]),
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("1364-2001", [KW_automatic, KW_endgenerate, KW_generate, KW_genvar,
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KW_localparam, KW_noshowcancelled, KW_pulsestyle_ondetect,
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KW_pulsestyle_onevent, KW_showcancelled, KW_signed, KW_unsigned]),
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("1364-2005", [KW_uwire]),
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("1800-2005", [KW_alias, KW_always_comb, KW_always_ff, KW_always_latch,
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KW_assert, KW_assume, KW_before, KW_bind, KW_bins, KW_binsof, KW_bit,
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KW_break, KW_byte, KW_chandle, KW_class, KW_clocking, KW_const,
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KW_constraint, KW_context, KW_continue, KW_cover, KW_covergroup,
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KW_coverpoint, KW_cross, KW_dist, KW_do, KW_endclass, KW_endclocking,
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KW_endgroup, KW_endinterface, KW_endpackage, KW_endprogram, KW_endproperty,
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KW_endsequence, KW_enum, KW_expect, KW_export, KW_extends, KW_extern,
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KW_final, KW_first_match, KW_foreach, KW_forkjoin, KW_iff, KW_ignore_bins,
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KW_illegal_bins, KW_import, KW_inside, KW_int, KW_interface, KW_intersect,
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KW_join_any, KW_join_none, KW_local, KW_logic, KW_longint, KW_matches,
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KW_modport, KW_new, KW_null, KW_package, KW_packed, KW_priority, KW_program,
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KW_property, KW_protected, KW_pure, KW_rand, KW_randc, KW_randcase,
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KW_randsequence, KW_ref, KW_return, KW_sequence, KW_shortint, KW_shortreal,
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KW_solve, KW_static, KW_string, KW_struct, KW_super, KW_tagged, KW_this,
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KW_throughout, KW_timeprecision, KW_timeunit, KW_type, KW_typedef, KW_union,
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KW_unique, KW_var, KW_virtual, KW_void, KW_wait_order, KW_wildcard, KW_with,
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KW_within]),
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("1800-2009", [KW_accept_on, KW_checker, KW_endchecker, KW_eventually,
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KW_global, KW_implies, KW_let, KW_nexttime, KW_reject_on, KW_restrict,
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KW_s_always, KW_s_eventually, KW_s_nexttime, KW_s_until, KW_s_until_with,
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KW_strong, KW_sync_accept_on, KW_sync_reject_on, KW_unique0, KW_until,
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KW_until_with, KW_untyped, KW_weak]),
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("1800-2012", [KW_implements, KW_nettype, KW_interconnect, KW_soft]),
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("1800-2017", [])
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]
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specMap :: Map.Map String (Set.Set TokenName)
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specMap =
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Map.fromList $ zip keys vals
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where
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keys = map fst newKeywords
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sets = map (Set.fromList . snd) newKeywords
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allKeywords = Set.unions sets
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vals =
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map (Set.difference allKeywords) $
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scanl1 Set.union sets
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@ -33,9 +33,11 @@ import System.FilePath (dropFileName)
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import System.Directory (findFile)
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import System.IO.Unsafe (unsafePerformIO)
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import qualified Data.Map.Strict as Map
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import qualified Data.Set as Set
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import Data.List (span, elemIndex, dropWhileEnd)
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import Data.Maybe (isJust, fromJust)
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import Language.SystemVerilog.Parser.Keywords (specMap)
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import Language.SystemVerilog.Parser.Tokens
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}
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@ -513,13 +515,14 @@ data AlexUserState = LS
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, lsEnv :: Env -- active macro definitions
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, lsCondStack :: [Cond] -- if-else cascade state
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, lsIncludePaths :: [FilePath] -- folders to search for includes
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, lsSpecStack :: [Set.Set TokenName] -- stack of non-keyword token names
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} deriving (Eq, Show)
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-- this initial user state does not contain the initial filename, environment,
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-- or include paths; alex requires that this be defined; we override it before
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-- we begin the actual lexing procedure
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alexInitUserState :: AlexUserState
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alexInitUserState = LS [] "" Map.empty [] []
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alexInitUserState = LS [] "" Map.empty [] [] []
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-- public-facing lexer entrypoint
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lexFile :: [String] -> Env -> FilePath -> IO (Either String ([Token], Env))
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@ -529,10 +532,14 @@ lexFile includePaths env path = do
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return $ case result of
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Left msg -> Left msg
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Right finalState ->
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if null $ lsCondStack finalState
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then Right (finalToks, lsEnv finalState)
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else Left $ path ++ ": unfinished conditional directives: " ++
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(show $ length $ lsCondStack finalState)
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if not $ null $ lsCondStack finalState then
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Left $ path ++ ": unfinished conditional directives: " ++
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(show $ length $ lsCondStack finalState)
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else if not $ null $ lsSpecStack finalState then
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Left $ path ++ ": unterminated begin_keywords blocks: " ++
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(show $ length $ lsSpecStack finalState)
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else
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Right (finalToks, lsEnv finalState)
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where finalToks = coalesce $ reverse $ lsToks finalState
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where
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setEnv = do
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@ -910,6 +917,27 @@ handleDirective (posOrig, _, _, strOrig) len = do
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"pragma" -> passThrough
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"resetall" -> passThrough
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"begin_keywords" -> do
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quotedSpec <- takeQuotedString
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let spec = tail $ init quotedSpec
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case Map.lookup spec specMap of
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Nothing ->
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lexicalError $ "invalid keyword set name: " ++ show spec
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Just set -> do
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specStack <- gets lsSpecStack
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modify $ \s -> s { lsSpecStack = set : specStack }
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dropWhitespace
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alexMonadScan
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"end_keywords" -> do
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specStack <- gets lsSpecStack
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if null specStack
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then
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lexicalError "unexpected end_keywords before begin_keywords"
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else do
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modify $ \s -> s { lsSpecStack = tail specStack }
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dropWhitespace
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alexMonadScan
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"__FILE__" -> do
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tokPos <- toTokPos posOrig
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currFile <- gets lsCurrFile
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@ -1070,7 +1098,11 @@ tok tokId (pos, _, _, input) len = do
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tokPos <- toTokPos pos
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condStack <- gets lsCondStack
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() <- if any (/= CurrentlyTrue) condStack
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then modify id
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else modify (push $ Token tokId tokStr tokPos)
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then return ()
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else do
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specStack <- gets lsSpecStack
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if null specStack || Set.notMember tokId (head specStack)
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then modify (push $ Token tokId tokStr tokPos)
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else modify (push $ Token Id_simple ('_' : tokStr) tokPos)
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alexMonadScan
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}
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@ -381,4 +381,4 @@ data TokenName
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| Spe_Directive
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| Unknown
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| MacroBoundary
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deriving (Show, Eq)
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deriving (Show, Eq, Ord)
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@ -48,6 +48,7 @@ executable sv2v
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Language.SystemVerilog.AST.Stmt
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Language.SystemVerilog.AST.Type
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Language.SystemVerilog.Parser
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Language.SystemVerilog.Parser.Keywords
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Language.SystemVerilog.Parser.Lex
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Language.SystemVerilog.Parser.Parse
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Language.SystemVerilog.Parser.ParseDecl
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@ -0,0 +1,16 @@
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`begin_keywords "1364-2001-noconfig"
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task foo;
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integer automatic = 2;
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$display(automatic * automatic);
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endtask
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`begin_keywords "1364-2005"
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task automatic bar;
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integer logic = 3;
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$display(logic * logic);
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endtask
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`end_keywords
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`end_keywords
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module top;
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initial foo;
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initial bar;
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endmodule
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@ -0,0 +1,18 @@
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module top;
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task foo;
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integer x;
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begin
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x = 2;
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$display(x * x);
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end
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endtask
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task bar;
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integer y;
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begin
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y = 3;
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$display(y * y);
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end
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endtask
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initial foo;
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initial bar;
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endmodule
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