mirror of https://github.com/zachjs/sv2v.git
preliminary support for generators
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Zachary Snow
parent
b0d573c51f
commit
06b47b06ee
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@ -15,9 +15,11 @@ module Language.SystemVerilog.AST
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, Parameter (..)
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, Localparam (..)
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, IntegerV (..)
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, GenItem (..)
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, PortBinding
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, Case
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, Range
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, GenCase
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) where
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import Data.Bits
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@ -85,6 +87,8 @@ data ModuleItem
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| Assign LHS Expr
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| Instance Identifier [PortBinding] Identifier [PortBinding]
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| Function (Maybe FuncRet) Identifier [(Bool, BlockItemDeclaration)] Stmt
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| Genvar Identifier
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| Generate [GenItem]
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deriving Eq
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-- "function inputs and outputs are inferred to be of type reg if no internal
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@ -119,6 +123,8 @@ instance Show ModuleItem where
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| null params -> printf "%s %s %s;" m i (showPorts show ports)
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| otherwise -> printf "%s #%s %s %s;" m (showPorts show params) i (showPorts show ports)
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Function t x i b -> printf "function %s%s;\n%s\n%s\nendfunction" (showFuncRet t) x (indent $ unlines' $ map showFunctionItem i) (indent $ show b)
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Genvar x -> printf "genvar %s;" x
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Generate b -> printf "generate\n%s\nendgenerate" (indent $ unlines' $ map show b)
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where
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showPorts :: (Expr -> String) -> [(Identifier, Maybe Expr)] -> String
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showPorts s ports = indentedParenList [ if i == "" then show (fromJust arg) else printf ".%s(%s)" i (if isJust arg then s $ fromJust arg else "") | (i, arg) <- ports ]
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@ -332,7 +338,7 @@ instance Show BlockItemDeclaration where
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type Case = ([Expr], Stmt)
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showCase :: Case -> String
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showCase :: (Show x, Show y) => ([x], y) -> String
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showCase (a, b) = printf "%s:\n%s" (commas $ map show a) (indent $ show b)
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data Call = Call Identifier [Expr] deriving Eq
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@ -362,3 +368,26 @@ indentedParenList [] = "()"
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indentedParenList [x] = "(" ++ x ++ ")"
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indentedParenList l =
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"(\n" ++ (indent $ intercalate ",\n" l) ++ "\n)"
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type GenCase = ([Expr], GenItem)
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data GenItem
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= GenBlock (Maybe Identifier) [GenItem]
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| GenCase Expr [GenCase] (Maybe GenItem)
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| GenFor (Identifier, Expr) Expr (Identifier, Expr) Identifier [GenItem]
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| GenIf Expr GenItem GenItem
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| GenNull
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| GenModuleItem ModuleItem
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deriving Eq
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instance Show GenItem where
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showList i _ = unlines' $ map show i
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show (GenBlock Nothing i) = printf "begin\n%s\nend" (indent $ unlines' $ map show i)
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show (GenBlock (Just x) i) = printf "begin : %s\n%s\nend" x (indent $ unlines' $ map show i)
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show (GenCase e c Nothing ) = printf "case (%s)\n%s\nendcase" (show e) (indent $ unlines' $ map showCase c)
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show (GenCase e c (Just d)) = printf "case (%s)\n%s\n\tdefault:\n%s\nendcase" (show e) (indent $ unlines' $ map showCase c) (indent $ indent $ show d)
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show (GenIf e a GenNull) = printf "if (%s)\n%s" (show e) (indent $ show a)
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show (GenIf e a b ) = printf "if (%s)\n%s\nelse\n%s" (show e) (indent $ show a) (indent $ show b)
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show (GenFor (x1, e1) c (x2, e2) x is) = printf "for (%s = %s; %s; %s = %s) %s" x1 (show e1) (show c) x2 (show e2) (show $ GenBlock (Just x) is)
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show GenNull = ";"
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show (GenModuleItem item) = show item
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@ -67,8 +67,11 @@ tokens :-
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"endcase" { tok KW_endcase }
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"endmodule" { tok KW_endmodule }
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"endfunction" { tok KW_endfunction}
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"endgenerate" { tok KW_endgenerate}
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"function" { tok KW_function }
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"for" { tok KW_for }
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"generate" { tok KW_generate }
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"genvar" { tok KW_genvar }
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"if" { tok KW_if }
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"initial" { tok KW_initial }
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"inout" { tok KW_inout }
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@ -27,9 +27,12 @@ import Language.SystemVerilog.Parser.Tokens
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"end" { Token KW_end _ _ }
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"endcase" { Token KW_endcase _ _ }
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"endfunction" { Token KW_endfunction _ _ }
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"endgenerate" { Token KW_endgenerate _ _ }
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"endmodule" { Token KW_endmodule _ _ }
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"function" { Token KW_function _ _ }
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"for" { Token KW_for _ _ }
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"generate" { Token KW_generate _ _ }
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"genvar" { Token KW_genvar _ _ }
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"if" { Token KW_if _ _ }
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"initial" { Token KW_initial _ _ }
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"inout" { Token KW_inout _ _ }
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@ -224,6 +227,8 @@ ModuleItem :: { [ModuleItem] }
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| "always" opt(EventControl) Stmt { [Always $2 $3] }
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| Identifier ParameterBindings Identifier Bindings ";" { [Instance $1 $2 $3 $4] }
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| "function" opt(RangeOrType) Identifier FunctionItems Stmt "endfunction" { [Function $2 $3 $4 $5] }
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| "genvar" Identifiers ";" { map Genvar $2 }
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| "generate" GenItems "endgenerate" { [Generate $2] }
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FunctionItems :: { [(Bool, BlockItemDeclaration)] }
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: "(" FunctionPortList ";" BlockItemDeclarations { (map ((,) True) $2) ++ (map ((,) False) $4) }
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@ -331,8 +336,7 @@ Stmt :: { Stmt }
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| "for" "(" Identifier "=" Expr ";" Expr ";" Identifier "=" Expr ")" Stmt { For ($3, $5) $7 ($9, $11) $13 }
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| LHS "=" Expr ";" { BlockingAssignment $1 $3 }
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| LHS "<=" Expr ";" { NonBlockingAssignment $1 $3 }
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-- | Call ";" { StmtCall $1 }
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| "case" "(" Expr ")" Cases CaseDefault "endcase" { Case $3 $5 $6 }
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| "case" "(" Expr ")" Cases opt(CaseDefault) "endcase" { Case $3 $5 $6 }
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BlockItemDeclarations :: { [BlockItemDeclaration] }
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: BlockItemDeclaration { $1 }
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@ -351,15 +355,14 @@ BlockVariableType :: { (Identifier, [Range]) }
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| Identifier Dimensions { ($1, $2) }
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Cases :: { [Case] }
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: { [] }
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| Cases Case { $1 ++ [$2] }
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: {- empty -} { [] }
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| Cases Case { $1 ++ [$2] }
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Case :: { Case }
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: Exprs ":" Stmt { ($1, $3) }
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: Exprs ":" Stmt { ($1, $3) }
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CaseDefault :: { Maybe Stmt }
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: { Nothing }
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| "default" ":" Stmt { Just $3 }
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CaseDefault :: { Stmt }
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: "default" opt(":") Stmt { $3 }
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Number :: { String }
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: number { tokenString $1 }
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@ -424,6 +427,34 @@ Expr :: { Expr }
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| "~^" Expr %prec RedOps { UniOp RedXnor $2 }
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| "^~" Expr %prec RedOps { UniOp RedXnor $2 }
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GenItemOrNull :: { GenItem }
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: GenItem { $1 }
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| ";" { GenNull }
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GenItems :: { [GenItem] }
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: {- empty -} { [] }
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| GenItems GenItem { $1 ++ [$2] }
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GenItem :: { GenItem }
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: "if" "(" Expr ")" GenItemOrNull "else" GenItemOrNull { GenIf $3 $5 $7 }
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| "if" "(" Expr ")" GenItemOrNull %prec NoElse { GenIf $3 $5 GenNull }
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| "begin" GenItems "end" { GenBlock Nothing $2 }
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| "begin" ":" Identifier GenItems "end" { GenBlock (Just $3) $4 }
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| "case" "(" Expr ")" GenCases opt(GenCaseDefault) "endcase" { GenCase $3 $5 $6 }
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| "for" "(" Identifier "=" Expr ";" Expr ";" Identifier "=" Expr ")" "begin" ":" Identifier GenItems "end" { GenFor ($3, $5) $7 ($9, $11) $15 $16 }
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-- TODO: We should restrict it to the module items that are actually allowed.
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| ModuleItem { genItemsToGenItem $ map GenModuleItem $1 }
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GenCases :: { [GenCase] }
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: {- empty -} { [] }
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| GenCases GenCase { $1 ++ [$2] }
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GenCase :: { GenCase }
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: Exprs ":" GenItemOrNull { ($1, $3) }
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GenCaseDefault :: { GenItem }
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: "default" opt(":") GenItemOrNull { $3 }
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{
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parseError :: [Token] -> a
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@ -465,5 +496,14 @@ stmtsToStmt [] = error "stmtsToStmt given empty list!"
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stmtsToStmt [s] = s
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stmtsToStmt ss = Block Nothing ss
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moduleItemsToSingleGenItem :: [ModuleItem] -> GenItem
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moduleItemsToSingleGenItem [x] = GenModuleItem x
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moduleItemsToSingleGenItem other = error $ "multiple module items in a generate block where only one was allowed" ++ show other
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genItemsToGenItem :: [GenItem] -> GenItem
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genItemsToGenItem [] = error "genItemsToGenItem given empty list!"
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genItemsToGenItem [x] = x
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genItemsToGenItem xs = GenBlock Nothing xs
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}
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