mirror of https://github.com/zachjs/sv2v.git
removed BitVec exprs to preserve number formatting
This commit is contained in:
Zachary Snow
parent
a3937a2719
commit
b0d573c51f
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@ -1,66 +0,0 @@
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-- | Unsigned bit vectors.
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module Data.BitVec
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( BitVec
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, bitVec
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, select
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, width
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, value
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) where
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import Data.Bits
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data BitVec = BitVec Int Integer deriving (Show, Eq)
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instance Num BitVec where
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BitVec w1 v1 + BitVec w2 v2 = bitVec (max w1 w2) (v1 + v2)
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BitVec w1 v1 - BitVec w2 v2 = bitVec (max w1 w2) (v1 - v2)
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BitVec w1 v1 * BitVec w2 v2 = bitVec (max w1 w2) (v1 * v2)
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abs = id
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signum (BitVec _ v) = if v == 0 then bitVec 1 0 else bitVec 1 1
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fromInteger i = bitVec (wid i) i
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where
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wid :: Integer -> Int
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wid a
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| a == 0 = 0
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| a == -1 = 1
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| otherwise = 1 + wid (shiftR a 1)
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instance Bits BitVec where
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BitVec w1 v1 .&. BitVec w2 v2 = bitVec (max w1 w2) (v1 .&. v2)
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BitVec w1 v1 .|. BitVec w2 v2 = bitVec (max w1 w2) (v1 .|. v2)
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BitVec w1 v1 `xor` BitVec w2 v2 = bitVec (max w1 w2) (v1 `xor` v2)
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complement (BitVec w v) = bitVec w $ complement v
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shift (BitVec w v) i = bitVec w $ shift v i
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rotate _ _ = undefined --XXX To lazy to implemented it now.
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bit i = fromInteger $ bit i
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testBit (BitVec _ v) i = testBit v i
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bitSize (BitVec w _) = w
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bitSizeMaybe (BitVec w _) = Just w
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isSigned _ = False
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popCount (BitVec _ v) = popCount v
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instance Semigroup BitVec where
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(<>) = mappend
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instance Monoid BitVec where
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mempty = BitVec 0 0
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mappend (BitVec w1 v1) (BitVec w2 v2) = BitVec (w1 + w2) (shiftL v1 w2 .|. v2)
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-- | BitVec construction, given width and value.
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bitVec :: Int -> Integer -> BitVec
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bitVec w v = BitVec w' $ v .&. ((2 ^ fromIntegral w') - 1)
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where
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w' = max w 0
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-- | Bit seclection. LSB is 0.
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select :: BitVec -> (BitVec, BitVec) -> BitVec
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select (BitVec _ v) (msb, lsb) = bitVec (fromIntegral $ value $ msb - lsb + 1) $ shiftR v (fromIntegral $ value $ lsb)
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-- | Width of a 'BitVec'.
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width :: BitVec -> Int
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width (BitVec w _) = w
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-- | Value of a 'BitVec'.
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value :: BitVec -> Integer
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value (BitVec _ v) = v
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@ -25,8 +25,6 @@ import Data.List
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import Data.Maybe
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import Text.Printf
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import Data.BitVec
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type Identifier = String
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-- Note: Verilog allows modules to be declared with either a simple list of
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@ -96,11 +94,11 @@ type PortBinding = (Identifier, Maybe Expr)
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data Parameter = Parameter (Maybe Range) Identifier Expr deriving Eq
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instance Show Parameter where
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show (Parameter r n e) = printf "parameter %s%s = %s;" (showRange r) n (showExprConst e)
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show (Parameter r n e) = printf "parameter %s%s = %s;" (showRange r) n (show e)
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data Localparam = Localparam (Maybe Range) Identifier Expr deriving Eq
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instance Show Localparam where
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show (Localparam r n e) = printf "localparam %s%s = %s;" (showRange r) n (showExprConst e)
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show (Localparam r n e) = printf "localparam %s%s = %s;" (showRange r) n (show e)
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data IntegerV = IntegerV Identifier RangesOrAssignment deriving Eq
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instance Show IntegerV where
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@ -119,7 +117,7 @@ instance Show ModuleItem where
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Assign a b -> printf "assign %s = %s;" (show a) (show b)
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Instance m params i ports
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| null params -> printf "%s %s %s;" m i (showPorts show ports)
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| otherwise -> printf "%s #%s %s %s;" m (showPorts showExprConst params) i (showPorts show ports)
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| otherwise -> printf "%s #%s %s %s;" m (showPorts show params) i (showPorts show ports)
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Function t x i b -> printf "function %s%s;\n%s\n%s\nendfunction" (showFuncRet t) x (indent $ unlines' $ map showFunctionItem i) (indent $ show b)
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where
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showPorts :: (Expr -> String) -> [(Identifier, Maybe Expr)] -> String
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@ -151,7 +149,7 @@ showRanges = concat . (map rangeToString)
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showRange :: Maybe Range -> String
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showRange Nothing = ""
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showRange (Just (h, l)) = printf "[%s:%s] " (showExprConst h) (showExprConst l)
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showRange (Just (h, l)) = printf "[%s:%s] " (show h) (show l)
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indent :: String -> String
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indent a = '\t' : f a
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@ -166,7 +164,7 @@ unlines' = intercalate "\n"
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data Expr
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= String String
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| Number BitVec
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| Number String
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| ConstBool Bool
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| Ident Identifier
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| IdentRange Identifier Range
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@ -247,43 +245,21 @@ instance Show BinOp where
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Gt -> ">"
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Ge -> ">="
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showBitVecDefault :: BitVec -> String
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showBitVecDefault a = printf "%d'h%x" (width a) (value a)
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showBitVecConst :: BitVec -> String
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showBitVecConst a = show $ value a
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instance Show Expr where show = showExpr showBitVecDefault
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showExprConst :: Expr -> String
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showExprConst = showExpr showBitVecConst
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showExpr :: (BitVec -> String) -> Expr -> String
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showExpr bv x = case x of
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String a -> printf "\"%s\"" a
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Number a -> bv a
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ConstBool a -> printf "1'b%s" (if a then "1" else "0")
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Ident a -> a
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IdentBit a b -> printf "%s[%s]" a (showExprConst b)
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IdentRange a (b, c) -> printf "%s[%s:%s]" a (showExprConst b) (showExprConst c)
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Repeat a b -> printf "{%s {%s}}" (showExprConst a) (commas $ map s b)
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Concat a -> printf "{%s}" (commas $ map show a)
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ExprCall a -> show a
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UniOp a b -> printf "(%s %s)" (show a) (s b)
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BinOp a b c -> printf "(%s %s %s)" (s b) (show a) (s c)
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Mux a b c -> printf "(%s ? %s : %s)" (s a) (s b) (s c)
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Bit a b -> printf "(%s [%d])" (s a) b
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where
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s = showExpr bv
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instance Num Expr where
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(+) = BinOp Add
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(-) = BinOp Sub
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(*) = BinOp Mul
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negate = UniOp USub
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abs = undefined
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signum = undefined
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fromInteger = Number . fromInteger
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instance Show Expr where
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show x = case x of
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String a -> printf "\"%s\"" a
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Number a -> a
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ConstBool a -> printf "1'b%s" (if a then "1" else "0")
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Ident a -> a
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IdentBit a b -> printf "%s[%s]" a (show b)
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IdentRange a (b, c) -> printf "%s[%s:%s]" a (show b) (show c)
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Repeat a b -> printf "{%s {%s}}" (show a) (commas $ map show b)
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Concat a -> printf "{%s}" (commas $ map show a)
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ExprCall a -> show a
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UniOp a b -> printf "(%s %s)" (show a) (show b)
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BinOp a b c -> printf "(%s %s %s)" (show b) (show a) (show c)
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Mux a b c -> printf "(%s ? %s : %s)" (show a) (show b) (show c)
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Bit a b -> printf "(%s [%d])" (show a) b
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instance Bits Expr where
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(.&.) = BinOp BWAnd
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@ -299,14 +275,6 @@ instance Bits Expr where
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bit = error "Not supported: bit"
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popCount = error "Not supported: popCount"
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instance Semigroup Expr where
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(<>) = mappend
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instance Monoid Expr where
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mempty = 0
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mappend a b = mconcat [a, b]
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mconcat = Concat
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data LHS
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= LHS Identifier
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| LHSBit Identifier Expr
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@ -316,8 +284,8 @@ data LHS
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instance Show LHS where
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show (LHS a ) = a
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show (LHSBit a b ) = printf "%s[%s]" a (showExprConst b)
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show (LHSRange a (b, c)) = printf "%s[%s:%s]" a (showExprConst b) (showExprConst c)
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show (LHSBit a b ) = printf "%s[%s]" a (show b)
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show (LHSRange a (b, c)) = printf "%s[%s:%s]" a (show b) (show c)
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show (LHSConcat a ) = printf "{%s}" (commas $ map show a)
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data Stmt
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@ -4,7 +4,6 @@ module Language.SystemVerilog.Parser.Parse (modules) where
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import Data.Bits
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import Data.List
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import Data.BitVec
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import Data.Maybe
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import Language.SystemVerilog.AST
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import Language.SystemVerilog.Parser.Tokens
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@ -362,8 +361,8 @@ CaseDefault :: { Maybe Stmt }
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: { Nothing }
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| "default" ":" Stmt { Just $3 }
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Number :: { BitVec }
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: number { toNumber $1 }
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Number :: { String }
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: number { tokenString $1 }
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String :: { String }
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: string { toString $1 }
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@ -435,25 +434,6 @@ parseError a = case a of
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toString :: Token -> String
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toString = tail . init . tokenString
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toNumber :: Token -> BitVec
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toNumber = number . tokenString
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where
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number :: String -> BitVec
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number a
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| all (flip elem ['0' .. '9']) a = fromInteger $ read a
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| head a == '\'' = fromInteger $ f a
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| isInfixOf "'" a = bitVec (read w) (f b)
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| otherwise = error $ "Invalid number format: " ++ a
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where
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w = takeWhile (/= '\'') a
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b = dropWhile (/= '\'') a
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f a
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| isPrefixOf "'d" a = read $ drop 2 a
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| isPrefixOf "'h" a = read $ "0x" ++ drop 2 a
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| isPrefixOf "'b" a = foldl (\ n b -> shiftL n 1 .|. (if b == '1' then 1 else 0)) 0 (drop 2 a)
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| otherwise = error $ "Invalid number format: " ++ a
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portDeclToModuleItems
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:: Direction
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-> (Maybe ((Maybe Range) -> Type))
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@ -31,7 +31,6 @@ library
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array >= 0.5.1.0 && < 0.6
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exposed-modules:
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Data.BitVec
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Language.SystemVerilog
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Language.SystemVerilog.AST
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Language.SystemVerilog.Parser
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@ -52,7 +51,6 @@ executable sv2v
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array,
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base
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other-modules:
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Data.BitVec
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Language.SystemVerilog
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Language.SystemVerilog.AST
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Language.SystemVerilog.Parser
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