sv2v/test/basic/logic_cond.v

module Example(inp, out);
    parameter ENABLED = 1;
    localparam [0:0] DEFAULT = 1'b0;
    input wire inp;
    output reg out;
    generate
        if (ENABLED)
            always @* out = inp;
        else
            initial out = DEFAULT;
    endgenerate
endmodule
fix converted constant continuous assignment 2020-11-25 01:27:58 +01:00			`module Example(inp, out);`
			`parameter ENABLED = 1;`
improved portability of logic conversion - indirect converted reg continuous assignments through wires - fix typeof for implicitly typed ports - fix typeof for sized implicitly typed params 2021-01-26 01:23:54 +01:00			`localparam [0:0] DEFAULT = 1'b0;`
fix converted constant continuous assignment 2020-11-25 01:27:58 +01:00			`input wire inp;`
			`output reg out;`
			`generate`
			`if (ENABLED)`
			`always @* out = inp;`
			`else`
improved portability of logic conversion - indirect converted reg continuous assignments through wires - fix typeof for implicitly typed ports - fix typeof for sized implicitly typed params 2021-01-26 01:23:54 +01:00			`initial out = DEFAULT;`
fix converted constant continuous assignment 2020-11-25 01:27:58 +01:00			`endgenerate`
			`endmodule`