mirror of https://github.com/zachjs/sv2v.git
12 lines
228 B
Verilog
12 lines
228 B
Verilog
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module Example(inp, out);
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parameter ENABLED = 1;
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input wire inp;
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output reg out;
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generate
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if (ENABLED)
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always @* out = inp;
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else
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initial out = 0;
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endgenerate
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endmodule
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