fix converted constant continuous assignment

src/Convert/Logic.hs

@@ -106,9 +106,21 @@ traverseModuleItem ports scopes =
         fixModuleItem :: ModuleItem -> ModuleItem
         -- rewrite bad continuous assignments to use procedural assignments
         fixModuleItem (Assign AssignOptionNone lhs expr) =
-            if not (isReg lhs)
-                then Assign AssignOptionNone lhs expr
-                else AlwaysC AlwaysComb $ Asgn AsgnOpEq Nothing lhs expr
+            if not (isReg lhs) then
+                Assign AssignOptionNone lhs expr
+            else if isConstant expr then
+                Initial $ Asgn AsgnOpEq Nothing lhs expr
+            else
+                AlwaysC AlwaysComb $ Asgn AsgnOpEq Nothing lhs expr
+            where
+                -- only handles expressions which are trivially constant for now
+                isConstant :: Expr -> Bool
+                isConstant Number{} = True
+                isConstant (Repeat _ es) = all isConstant es
+                isConstant (Concat   es) = all isConstant es
+                isConstant (BinOp _ e1 e2) = isConstant e1 && isConstant e2
+                isConstant (UniOp _ e) = isConstant e
+                isConstant _ = False
         -- rewrite port bindings to use temporary nets where necessary
         fixModuleItem (Instance moduleName params instanceName rs bindings) =
             if null newItems

test/basic/logic_cond.sv

@@ -0,0 +1,9 @@
+module Example(inp, out);
+    parameter ENABLED = 1;
+    input logic inp;
+    output logic out;
+    if (ENABLED)
+        always_comb out = inp;
+    else
+        assign out = '0;
+endmodule

test/basic/logic_cond.v

@@ -0,0 +1,11 @@
+module Example(inp, out);
+    parameter ENABLED = 1;
+    input wire inp;
+    output reg out;
+    generate
+        if (ENABLED)
+            always @* out = inp;
+        else
+            initial out = 0;
+    endgenerate
+endmodule

test/basic/logic_cond_tb.v

@@ -0,0 +1,27 @@
+module top;
+    reg inp;
+
+    wire out1;
+    wire out2;
+    wire out3;
+
+    Example      m1(inp, out1);
+    Example #(0) m2(inp, out2);
+    Example #(1) m3(inp, out3);
+
+    task dump;
+        $display("%b %b %b %b", inp, out1, out2, out3);
+    endtask
+
+    initial begin
+        #1 dump();
+        inp = 0;
+        #1 dump();
+        inp = 1;
+        #1 dump();
+        inp = 1'bx;
+        #1 dump();
+        inp = 1'bz;
+        #1 dump();
+    end
+endmodule