mirror of https://github.com/zachjs/sv2v.git
12 lines
241 B
Verilog
12 lines
241 B
Verilog
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module top;
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initial begin : blk
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integer i;
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reg [1:0] y;
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reg x;
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for (i = 0; i < 3; i = i + 1) begin
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$display("%0d %b", 2, y);
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$display("%0d %b", 1, x);
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end
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end
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endmodule
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