mirror of https://github.com/zachjs/sv2v.git
fix overzealous task/function decl hoisting
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b8759776ca
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5c8d838eef
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@ -8,7 +8,7 @@
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module Convert.TFBlock (convert) where
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import Data.List (isPrefixOf)
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import Data.List (intersect, isPrefixOf)
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import Convert.Traverse
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import Language.SystemVerilog.AST
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@ -41,15 +41,35 @@ stmtsToStmt stmts = Block Seq "" [] stmts
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flattenOuterBlocks :: Stmt -> ([Decl], [Stmt])
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flattenOuterBlocks (Block Seq "" declsA [stmt]) =
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(declsA ++ declsB, stmtsB)
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if canCombine declsA declsB
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then (declsA ++ declsB, stmtsB)
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else (declsA, [stmt])
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where (declsB, stmtsB) = flattenOuterBlocks stmt
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flattenOuterBlocks (Block Seq "" declsA (Block Seq name declsB stmtsA : stmtsB)) =
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flattenOuterBlocks $ Block Seq name (declsA ++ declsB) (stmtsA ++ stmtsB)
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if canCombine declsA declsB
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then flattenOuterBlocks $
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Block Seq name (declsA ++ declsB) (stmtsA ++ stmtsB)
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else (declsA, Block Seq name declsB stmtsA : stmtsB)
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flattenOuterBlocks (Block Seq name decls stmts)
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| notscope name = (decls, stmts)
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| otherwise = ([], [Block Seq name decls stmts])
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flattenOuterBlocks stmt = ([], [stmt])
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canCombine :: [Decl] -> [Decl] -> Bool
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canCombine [] _ = True
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canCombine _ [] = True
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canCombine declsA declsB =
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null $ intersect (declNames declsA) (declNames declsB)
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declNames :: [Decl] -> [Identifier]
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declNames = filter (not . null) . map declName
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declName :: Decl -> Identifier
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declName (Variable _ _ x _ _) = x
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declName (Param _ _ x _) = x
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declName (ParamType _ x _) = x
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declName CommentDecl{} = ""
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notscope :: Identifier -> Bool
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notscope "" = True
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notscope name = "sv2v_autoblock_" `isPrefixOf` name
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@ -0,0 +1,22 @@
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`define TEST \
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reg x; \
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begin \
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reg [1:0] x; \
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$display("%0d %b", $bits(x), x); \
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end \
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$display("%0d %b", $bits(x), x);
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module top;
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task t;
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input integer unused;
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`TEST
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endtask
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function f;
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input integer unused;
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`TEST
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endfunction
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initial t(f(0));
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initial begin
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`TEST
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end
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endmodule
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@ -0,0 +1,11 @@
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module top;
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initial begin : blk
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integer i;
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reg [1:0] y;
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reg x;
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for (i = 0; i < 3; i = i + 1) begin
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$display("%0d %b", 2, y);
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$display("%0d %b", 1, x);
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end
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end
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endmodule
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