mirror of https://github.com/zachjs/sv2v.git
28 lines
784 B
Verilog
28 lines
784 B
Verilog
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module Module(xs);
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parameter LEFT = 0;
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parameter RIGHT = 0;
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input wire [LEFT:RIGHT] xs;
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endmodule
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module Instance();
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parameter LEFT = 0;
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parameter RIGHT = 0;
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parameter INNER_LEFT = 0;
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parameter INNER_RIGHT = 0;
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parameter INNER_OFFSET = 0;
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reg [LEFT:RIGHT] xs;
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localparam LO = INNER_LEFT >= INNER_RIGHT ? INNER_RIGHT : INNER_LEFT;
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localparam HI = INNER_LEFT >= INNER_RIGHT ? INNER_LEFT : INNER_RIGHT;
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localparam LEN = HI - LO + 1;
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Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
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l(xs[INNER_LEFT:INNER_RIGHT]);
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Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
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m(xs[LO+:LEN]);
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Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
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n(xs[HI-:LEN]);
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endmodule
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