mirror of https://github.com/zachjs/sv2v.git
interface and instance array support
- support for interface instance arrays - support for interface-using module instance arrays - support for modport array bindings - fix modport bindings shadowed in nested instances
This commit is contained in:
Zachary Snow
parent
8eac9b0149
commit
2b377cef04
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@ -1,3 +1,4 @@
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{-# LANGUAGE PatternSynonyms #-}
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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@ -11,6 +12,7 @@ import Data.Maybe (mapMaybe)
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import Control.Monad.Writer.Strict
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import qualified Data.Map.Strict as Map
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import Convert.ExprUtils (endianCondExpr)
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import Convert.Scoper
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import Convert.Traverse
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import Language.SystemVerilog.AST
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@ -23,18 +25,34 @@ data PartInfo = PartInfo
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type PartInfos = Map.Map Identifier PartInfo
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type ModportInstances = [(Identifier, (Identifier, Identifier))]
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type ModportBinding = (Identifier, (Expr, Expr))
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type ModportBinding = (Identifier, (Substitutions, Expr))
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type Substitutions = [(Expr, Expr)]
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convert :: [AST] -> [AST]
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convert =
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traverseFiles (collectDescriptionsM collectPart)
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(map . convertDescription)
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convert files =
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if needsFlattening
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then files
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else traverseFiles
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(collectDescriptionsM collectPart)
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(map . convertDescription)
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files
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where
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-- we can only collect/map non-extern interfaces and modules
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collectPart :: Description -> Writer PartInfos ()
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collectPart (Part _ False kw _ name ports items) =
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tell $ Map.singleton name $ PartInfo kw ports items
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collectPart _ = return ()
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-- multidimensional instances need to be flattened before this
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-- conversion can proceed
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needsFlattening =
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getAny $ execWriter $ mapM (collectDescriptionsM checkPart) files
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checkPart :: Description -> Writer Any ()
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checkPart (Part _ _ _ _ _ _ items) =
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mapM (collectNestedModuleItemsM checkItem) items >> return ()
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checkPart _ = return ()
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checkItem :: ModuleItem -> Writer Any ()
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checkItem (Instance _ _ _ rs _) = when (length rs > 1) $ tell $ Any True
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checkItem _ = return ()
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convertDescription :: PartInfos -> Description -> Description
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convertDescription _ (Part _ _ Interface _ name _ _) =
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@ -54,26 +72,25 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
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traverseModuleItemM :: ModuleItem -> Scoper [ModportDecl] ModuleItem
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traverseModuleItemM (Modport modportName modportDecls) =
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insertElem modportName modportDecls >> return (Generate [])
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traverseModuleItemM (instanceItem @ (Instance _ _ _ [] _)) =
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traverseModuleItemM (instanceItem @ Instance{}) =
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if maybePartInfo == Nothing then
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return instanceItem
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else if partKind == Interface then
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-- inline instantiation of an interface
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convertNested $ Generate $ map GenModuleItem $
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inlineInstance [] []
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inlineInstance rs []
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partItems instanceName paramBindings portBindings
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else if not $ null (extractModportInstances partInfo) then do
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modports <- embedScopes (\l () -> l) ()
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-- inline instantiation of a module
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convertNested $ Generate $ map GenModuleItem $
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inlineInstance
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inlineInstance rs
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(modportBindings modports)
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(modportSubstitutions modports)
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partItems instanceName paramBindings portBindings
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else
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return instanceItem
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where
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Instance part rawParamBindings instanceName [] rawPortBindings =
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Instance part rawParamBindings instanceName rs rawPortBindings =
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instanceItem
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maybePartInfo = Map.lookup part parts
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Just partInfo = maybePartInfo
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@ -85,19 +102,73 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
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modportInstances = extractModportInstances partInfo
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modportBindings modports = mapMaybe
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(inferModportBinding modports modportInstances) portBindings
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modportSubstitutions modports = concatMap
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(expandModportBinding modports) (modportBindings modports)
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(inferModportBinding modports modportInstances) $
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map (second $ addImpliedSlice modports) portBindings
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second f = \(a, b) -> (a, f b)
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traverseModuleItemM other = return other
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-- determines the underlying modport and interface instances associated
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-- with the given port binding, if it is a modport binding
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-- add explicit slices for bindings of entire modport instance arrays
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addImpliedSlice :: Scopes [ModportDecl] -> Expr -> Expr
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addImpliedSlice modports (orig @ (Dot expr modportName)) =
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case lookupElem modports (InstArrKey expr) of
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Just (_, _, InstArrVal l r) ->
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Dot (Range expr NonIndexed (l, r)) modportName
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_ -> orig
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addImpliedSlice modports expr =
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case lookupElem modports (InstArrKey expr) of
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Just (_, _, InstArrVal l r) ->
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Range expr NonIndexed (l, r)
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_ -> expr
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-- elaborates and resolves provided modport bindings
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inferModportBinding :: Scopes [ModportDecl] -> ModportInstances ->
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PortBinding -> Maybe ModportBinding
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inferModportBinding _ _ ("", _) =
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error "internal inferModportBinding invariant violated"
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inferModportBinding modports modportInstances (portName, expr) =
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if maybeInfo == Nothing
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then Nothing
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else Just (portName, modportBinding)
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where
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modportBinding = (substitutions, replaceBit modportE)
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substitutions =
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genSubstitutions modports base instanceE modportE
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maybeInfo =
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lookupModportBinding modports modportInstances portName bitd
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Just (instanceE, modportE) = maybeInfo
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(exprUndot, bitd) = case expr of
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Dot subExpr x -> (subExpr, Dot bitdUndot x)
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_ -> (expr, bitdUndot)
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bitdUndot = case exprUndot of
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Range subExpr _ _ -> Bit subExpr taggedOffset
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Bit subExpr _ -> Bit subExpr untaggedOffset
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_ -> exprUndot
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bitReplacement = case exprUndot of
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Range _ mode range -> \e -> Range e mode range
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Bit _ idx -> flip Bit idx
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_ -> id
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base = case exprUndot of
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Range{} -> Bit (Ident portName) Tag
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_ -> Ident portName
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untaggedOffset = Ident $ modportBaseName portName
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taggedOffset = BinOp Add Tag untaggedOffset
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replaceBit :: Expr -> Expr
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replaceBit (Bit subExpr idx) =
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if idx == untaggedOffset || idx == taggedOffset
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then bitReplacement subExpr
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else Bit subExpr idx
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replaceBit (Dot subExpr x) =
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Dot (replaceBit subExpr) x
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replaceBit (Ident x) = Ident x
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replaceBit _ = error "replaceBit invariant violated"
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-- determines the underlying modport and interface instances associated
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-- with the given port binding, if it is a modport binding
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lookupModportBinding :: Scopes [ModportDecl] -> ModportInstances
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-> Identifier -> Expr -> Maybe (Expr, Expr)
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lookupModportBinding modports modportInstances portName expr =
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if bindingIsModport then
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-- provided specific instance modport
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foundModport expr
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@ -116,11 +187,11 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
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modportName = case lookup portName modportInstances of
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Just (_, x) -> x
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Nothing -> error $ "can't deduce modport for interface "
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++ " bound to port " ++ portName
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++ show expr ++ " bound to port " ++ portName
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foundModport modportE =
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Just (portName, (instanceE, modportE))
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where instanceE = findInstance modportE
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Just (findInstance modportE, qualifyModport modportE)
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findInstance :: Expr -> Expr
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findInstance e =
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case lookupElem modports (Dot e "") of
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@ -128,18 +199,27 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
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Bit e' _ -> findInstance e'
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Dot e' _ -> findInstance e'
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_ -> error "internal invariant violated"
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Just (accesses, _, _) ->
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foldl accessToExpr (Ident topName) rest
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where Access topName Nil : rest = init accesses
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Just (accesses, _, _) -> accessesToExpr $ init accesses
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qualifyModport :: Expr -> Expr
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qualifyModport e =
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case lookupElem modports e of
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Just (accesses, _, _) -> accessesToExpr accesses
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Nothing -> accessesToExpr $ init accesses
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where Just (accesses, _, _) =
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lookupElem modports (Dot e "")
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accessesToExpr :: [Access] -> Expr
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accessesToExpr accesses =
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foldl accessToExpr (Ident topName) rest
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where Access topName Nil : rest = accesses
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accessToExpr :: Expr -> Access -> Expr
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accessToExpr e (Access x Nil) = Dot e x
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accessToExpr e (Access x i) = Bit (Dot e x) i
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-- expand a modport binding into a series of expression substitutions
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expandModportBinding :: Scopes [ModportDecl]
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-> ModportBinding -> [(Expr, Expr)]
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expandModportBinding modports (portName, (instanceE, modportE)) =
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(Ident portName, instanceE) :
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genSubstitutions :: Scopes [ModportDecl] -> Expr -> Expr -> Expr
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-> [(Expr, Expr)]
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genSubstitutions modports baseE instanceE modportE =
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(baseE, instanceE) :
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map toPortBinding modportDecls
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where
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a = lookupElem modports modportE
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@ -148,7 +228,7 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
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if a == Nothing then b else a
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toPortBinding (_, x, e) = (x', e')
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where
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x' = Dot (Ident portName) x
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x' = Dot baseE x
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e' = prefixExpr e
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prefixExpr :: Expr -> Expr
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prefixExpr (Ident x) =
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@ -212,22 +292,29 @@ impliedModport =
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-- convert an interface-bound module instantiation or an interface instantiation
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-- into a series of equivalent inlined module items
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inlineInstance :: [ModportBinding] -> [(Expr, Expr)] -> [ModuleItem]
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inlineInstance :: [Range] -> [ModportBinding] -> [ModuleItem]
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-> Identifier -> [ParamBinding] -> [PortBinding] -> [ModuleItem]
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inlineInstance modportBindings modportSubstitutions items
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inlineInstance ranges modportBindings items
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instanceName instanceParams instancePorts =
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comment :
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map (MIPackageItem . Decl) bindingBaseParams ++
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map (MIPackageItem . Decl) parameterBinds ++
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Generate [GenBlock instanceName $ map GenModuleItem items']
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(wrapInstance $ GenBlock instanceName $ map GenModuleItem items')
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: portBindings
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where
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items' = evalScoper
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traverseDeclM traverseModuleItemM traverseGenItemM traverseStmtM ""
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$ map (traverseNestedModuleItems rewriteItem) $
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if null modportBindings
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then Modport "" (impliedModport items) : items
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then dimensionModport : bundleModport : items
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else items
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-- synthetic modports to be collected and removed after inlining
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bundleModport = Modport "" (impliedModport items)
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dimensionModport = if not isArray
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then MIPackageItem $ Decl $ CommentDecl "not an instance array"
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else InstArrEncoded arrayLeft arrayRight
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inlineKind =
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if null modportBindings
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then "interface"
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@ -239,7 +326,7 @@ inlineInstance modportBindings modportSubstitutions items
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filter notSubstituted instancePorts
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notSubstituted :: PortBinding -> Bool
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notSubstituted (portName, _) =
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lookup (portName) modportBindings == Nothing
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lookup portName modportBindings == Nothing
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rewriteItem :: ModuleItem -> ModuleItem
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rewriteItem =
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@ -273,6 +360,7 @@ inlineInstance modportBindings modportSubstitutions items
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traverseStmtLHSsM traverseLHSM
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-- used for replacing usages of modports in the module being inlined
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modportSubstitutions = concatMap (fst . snd) modportBindings
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lhsReplacements = map (\(x, y) -> (toLHS x, toLHS y)) exprReplacements
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exprReplacements = filter ((/= Nil) . snd) modportSubstitutions
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-- LHSs are replaced using simple substitutions
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@ -287,10 +375,21 @@ inlineInstance modportBindings modportSubstitutions items
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else traverseSinglyNestedLHSs (tagLHS scopes) lhs
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replaceLHS :: LHS -> LHS
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replaceLHS (LHSDot lhs "@") = lhs
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replaceLHS (LHSDot (LHSBit lhs elt) field) =
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case lookup (LHSDot (LHSBit lhs Tag) field) lhsReplacements of
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Just resolved -> replaceLHSArrTag elt resolved
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Nothing -> LHSDot (replaceLHS $ LHSBit lhs elt) field
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replaceLHS (LHSBit lhs elt) =
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case lookup (LHSBit lhs Tag) lhsReplacements of
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Just resolved -> replaceLHSArrTag elt resolved
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Nothing -> LHSBit (replaceLHS lhs) elt
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replaceLHS lhs =
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case lookup lhs lhsReplacements of
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Just lhs' -> lhs'
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Nothing -> traverseSinglyNestedLHSs replaceLHS lhs
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replaceLHSArrTag :: Expr -> LHS -> LHS
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replaceLHSArrTag =
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traverseNestedLHSs . (traverseLHSExprs . replaceArrTag)
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-- top-level expressions may be modports bound to other modports
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traverseExprM :: Expr -> Scoper Expr Expr
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traverseExprM expr = do
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@ -321,17 +420,40 @@ inlineInstance modportBindings modportSubstitutions items
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replaceExpr' expr
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replaceExpr' :: Expr -> Expr
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replaceExpr' (Dot expr "@") = expr
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replaceExpr' (Dot (Bit expr elt) field) =
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case lookup (Dot (Bit expr Tag) field) exprReplacements of
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Just resolved -> replaceArrTag (replaceExpr' elt) resolved
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Nothing -> Dot (replaceExpr' $ Bit expr elt) field
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replaceExpr' (Bit expr elt) =
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case lookup (Bit expr Tag) exprReplacements of
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Just resolved -> replaceArrTag (replaceExpr' elt) resolved
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Nothing -> Bit (replaceExpr' expr) (replaceExpr' elt)
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replaceExpr' expr =
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case lookup expr exprReplacements of
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Just expr' -> expr'
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Nothing -> traverseSinglyNestedExprs replaceExpr' expr
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replaceArrTag :: Expr -> Expr -> Expr
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replaceArrTag replacement Tag = replacement
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replaceArrTag replacement expr =
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traverseSinglyNestedExprs (replaceArrTag replacement) expr
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removeModportInstance :: ModuleItem -> ModuleItem
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removeModportInstance (MIPackageItem (Decl (Variable d t x a e))) =
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MIPackageItem $ Decl $
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if lookup x modportBindings /= Nothing
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then CommentDecl $ "removed modport instance " ++ x
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else Variable d t x a e
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if maybeModportBinding == Nothing then
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Variable d t x a e
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else if makeBindingBaseExpr modportE == Nothing then
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CommentDecl $ "removed modport instance " ++ x
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else if null a then
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localparam (modportBaseName x) bindingBaseExpr
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else
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localparam (modportBaseName x) $
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BinOp Sub bindingBaseExpr (sliceLo NonIndexed $ head a)
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where
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maybeModportBinding = lookup x modportBindings
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Just (_, modportE) = maybeModportBinding
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bindingBaseExpr = Ident $ bindingBaseName ++ x
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removeModportInstance other = other
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removeDeclDir :: ModuleItem -> ModuleItem
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@ -343,6 +465,26 @@ inlineInstance modportBindings modportSubstitutions items
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_ -> t
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removeDeclDir other = other
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-- capture the lower bound for each modport array binding
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bindingBaseParams = map makeBindingBaseParam modportBindings
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makeBindingBaseParam :: ModportBinding -> Decl
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makeBindingBaseParam (portName, (_, modportE)) =
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case makeBindingBaseExpr modportE of
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Just expr -> localparam (bindingBaseName ++ portName) expr
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Nothing -> CommentDecl "no-op"
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bindingBaseName = "_sv2v_bind_base_" ++ shortHash instanceName ++ "_"
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makeBindingBaseExpr :: Expr -> Maybe Expr
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makeBindingBaseExpr modportE =
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case modportE of
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Dot (Range _ mode range) _ -> Just $ sliceLo mode range
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Range _ mode range -> Just $ sliceLo mode range
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Dot (Bit _ idx) _ -> Just idx
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Bit _ idx -> Just idx
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_ -> Nothing
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localparam :: Identifier -> Expr -> Decl
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localparam = Param Localparam (Implicit Unspecified [])
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paramTmp = "_tmp_" ++ (shortHash (items, instanceName)) ++ "_"
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parameterBinds = map makeParameterBind instanceParams
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@ -371,10 +513,15 @@ inlineInstance modportBindings modportSubstitutions items
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portBindingItem :: PortBinding -> Maybe ModuleItem
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portBindingItem (_, Nil) = Nothing
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portBindingItem (ident, expr) =
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Just $ wrapInstance $ GenModuleItem $
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if findDeclDir ident == Input
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then bind (LHSDot (LHSIdent instanceName) ident) expr
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else bind (toLHS expr) (Dot (Ident instanceName) ident)
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where bind a b = Just $ Assign AssignOptionNone a b
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then bind (LHSDot (inj LHSBit LHSIdent) ident) expr
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else bind (toLHS expr) (Dot (inj Bit Ident) ident)
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where
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bind = Assign AssignOptionNone
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inj bit idn = if null ranges
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then idn instanceName
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else bit (idn instanceName) (Ident loopVar)
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declDirs = execWriter $
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mapM (collectDeclsM collectDeclDir) items
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@ -397,6 +544,50 @@ inlineInstance modportBindings modportSubstitutions items
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Nothing -> error $ "trying to bind an " ++ inlineKind
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++ " output to " ++ show expr ++ " but that can't be an LHS"
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-- for instance arrays, a unique identifier to be used as a genvar
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loopVar = "_sv2v_arr_" ++ shortHash (instanceName, ranges)
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isArray = not $ null ranges
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[arrayRange @ (arrayLeft, arrayRight)] = ranges
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-- wrap the given item in a generate loop if necessary
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wrapInstance :: GenItem -> ModuleItem
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wrapInstance item =
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Generate $
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if not isArray then
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[item]
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else
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[ GenModuleItem (Genvar loopVar)
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, GenFor inits cond incr item
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]
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where
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inits = (loopVar, arrayLeft)
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cond = endianCondExpr arrayRange
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(BinOp Ge (Ident loopVar) arrayRight)
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(BinOp Le (Ident loopVar) arrayRight)
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incr = (loopVar, AsgnOp Add, step)
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step = endianCondExpr arrayRange
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(UniOp UniSub $ RawNum 1) (RawNum 1)
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-- used for modport array binding offset placeholders
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pattern Tag :: Expr
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pattern Tag = Ident "%"
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modportBaseName :: Identifier -> Identifier
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modportBaseName = (++) "_sv2v_base_"
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-- the dimensions of interface instance arrays are encoded as synthetic modports
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-- during inlining, enabling subsequent modport bindings to implicitly use the
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-- bounds of the interface instance array when the bounds are unspecified
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pattern InstArrName :: Identifier
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pattern InstArrName = "~instance_array_dimensions~"
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pattern InstArrVal :: Expr -> Expr -> [ModportDecl]
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pattern InstArrVal l r = [(Local, "l", l), (Local, "r", r)]
|
||||
pattern InstArrKey :: Expr -> Expr
|
||||
pattern InstArrKey expr = Dot (Bit expr (RawNum 0)) InstArrName
|
||||
pattern InstArrEncoded :: Expr -> Expr -> ModuleItem
|
||||
pattern InstArrEncoded l r = Modport InstArrName (InstArrVal l r)
|
||||
|
||||
type Binding t = (Identifier, t)
|
||||
-- give a set of bindings explicit names
|
||||
resolveBindings :: Show t => [Identifier] -> [Binding t] -> [Binding t]
|
||||
|
|
@ -419,3 +610,9 @@ parameterNames =
|
|||
collectDeclM (Param Parameter _ x _) = tell [x]
|
||||
collectDeclM (ParamType Parameter x _) = tell [x]
|
||||
collectDeclM _ = return ()
|
||||
|
||||
-- determines the lower bound for the given slice
|
||||
sliceLo :: PartSelectMode -> Range -> Expr
|
||||
sliceLo NonIndexed (l, r) = endianCondExpr (l, r) r l
|
||||
sliceLo IndexedPlus (base, _) = base
|
||||
sliceLo IndexedMinus (base, len) = BinOp Add (BinOp Sub base len) (RawNum 1)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,173 @@
|
|||
interface Interface(i);
|
||||
input i;
|
||||
logic v;
|
||||
logic o;
|
||||
task tick;
|
||||
$display("I i = %b, v = %b, o = %b", i, v, o);
|
||||
endtask
|
||||
initial $display("Hello I'm Interface!");
|
||||
modport ModportA(
|
||||
input .i(i ^ 1'b1),
|
||||
output v
|
||||
);
|
||||
modport ModportB(
|
||||
input .i(i),
|
||||
output .v(o)
|
||||
);
|
||||
endinterface
|
||||
|
||||
module ModuleA(i);
|
||||
parameter flip = 0;
|
||||
Interface i;
|
||||
assign i.v = i.i ^ 1'(flip);
|
||||
task tick;
|
||||
$display("A i.v = %b", i.v);
|
||||
endtask
|
||||
initial $display("Hello I'm ModuleA %0d!", flip);
|
||||
endmodule
|
||||
|
||||
module ModuleASet(is);
|
||||
parameter flip2 = 0;
|
||||
parameter flip1 = 0;
|
||||
parameter flip0 = 0;
|
||||
Interface is [2:0];
|
||||
assign is[2].v = is[2].i ^ 1'(flip2);
|
||||
assign is[1].v = is[1].i ^ 1'(flip1);
|
||||
assign is[0].v = is[0].i ^ 1'(flip0);
|
||||
task tick;
|
||||
$display("AS i.v = %b", is[2].v);
|
||||
$display("AS i.v = %b", is[1].v);
|
||||
$display("AS i.v = %b", is[0].v);
|
||||
endtask
|
||||
initial begin
|
||||
$display("Hello I'm ModuleASet %0d %0d %0d!", flip2, flip1, flip0);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ModuleCSet(is);
|
||||
parameter flip2 = 0;
|
||||
parameter flip1 = 0;
|
||||
parameter flip0 = 0;
|
||||
Interface.ModportB is [2:0];
|
||||
assign is[2].v = is[2].i ^ 1'(flip2);
|
||||
assign is[1].v = is[1].i ^ 1'(flip1);
|
||||
assign is[0].v = is[0].i ^ 1'(flip0);
|
||||
task tick;
|
||||
$display("CS i.v = %b", is[2].v);
|
||||
$display("CS i.v = %b", is[1].v);
|
||||
$display("CS i.v = %b", is[0].v);
|
||||
endtask
|
||||
initial begin
|
||||
$display("Hello I'm ModuleCSet %0d %0d %0d!", flip2, flip1, flip0);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ModuleB(is);
|
||||
parameter WIDTH = 1;
|
||||
Interface is [WIDTH-1:0];
|
||||
logic [WIDTH-1:0] i_concat;
|
||||
logic [WIDTH-1:0] v_concat;
|
||||
for (genvar i = WIDTH - 1; i >= 0; i = i - 1) begin
|
||||
assign i_concat[i] = is[i].i;
|
||||
assign v_concat[i] = is[i].v;
|
||||
end
|
||||
task tick;
|
||||
$display("B i_concat = %b, v_concat = %b", i_concat, v_concat);
|
||||
bn.tick;
|
||||
endtask
|
||||
initial $display("Hello I'm ModuleB %0d!", WIDTH);
|
||||
ModuleBNested #(WIDTH) bn(is);
|
||||
endmodule
|
||||
|
||||
module ModuleBNested(is);
|
||||
parameter WIDTH = 1;
|
||||
Interface is [WIDTH-1:0];
|
||||
logic [WIDTH-1:0] i_concat;
|
||||
logic [WIDTH-1:0] v_concat;
|
||||
for (genvar i = WIDTH - 1; i >= 0; i = i - 1) begin
|
||||
assign i_concat[i] = is[i].i;
|
||||
assign v_concat[i] = is[i].v;
|
||||
end
|
||||
task tick;
|
||||
$display("BN i_concat = %b, v_concat = %b", i_concat, v_concat);
|
||||
endtask
|
||||
endmodule
|
||||
|
||||
module top;
|
||||
logic inp;
|
||||
|
||||
Interface intfX[2:0](inp);
|
||||
|
||||
ModuleA #(0) xa2(intfX[2]);
|
||||
ModuleA #(1) xa1(intfX[1]);
|
||||
ModuleA #(1) xa0(intfX[0]);
|
||||
|
||||
ModuleB #(3) xb20(intfX[2:0]);
|
||||
ModuleB #(2) xb21(intfX[2:1]);
|
||||
ModuleB #(1) xb22(intfX[2:2]);
|
||||
ModuleB #(1) xb11(intfX[1:1]);
|
||||
ModuleB #(1) xb00(intfX[0:0]);
|
||||
ModuleB #(3) xbf(intfX);
|
||||
|
||||
ModuleASet #(1, 1, 0) xs(intfX[2:0].ModportB);
|
||||
|
||||
Interface intfY[2:0](inp);
|
||||
|
||||
ModuleA #(0) ya2(intfY[2].ModportA);
|
||||
ModuleA #(1) ya1(intfY[1].ModportA);
|
||||
ModuleA #(1) ya0(intfY[0].ModportA);
|
||||
|
||||
ModuleB #(3) yb20(intfY[2:0].ModportA);
|
||||
ModuleB #(2) yb21(intfY[2:1].ModportA);
|
||||
ModuleB #(1) yb22(intfY[2:2].ModportA);
|
||||
ModuleB #(1) yb11(intfY[1:1].ModportA);
|
||||
ModuleB #(1) yb00(intfY[0:0].ModportA);
|
||||
ModuleB #(3) ybf(intfY.ModportA);
|
||||
|
||||
ModuleCSet #(0, 0, 1) ys(intfY[2:0]);
|
||||
|
||||
initial begin
|
||||
inp = 0; tick;
|
||||
inp = 1; tick;
|
||||
inp = 0; tick;
|
||||
inp = 1; tick;
|
||||
end
|
||||
|
||||
task tick;
|
||||
#1;
|
||||
|
||||
intfX[2].tick;
|
||||
intfX[1].tick;
|
||||
intfX[0].tick;
|
||||
|
||||
xa2.tick;
|
||||
xa1.tick;
|
||||
xa0.tick;
|
||||
|
||||
xb20.tick;
|
||||
xb21.tick;
|
||||
xb22.tick;
|
||||
xb11.tick;
|
||||
xb00.tick;
|
||||
xbf.tick;
|
||||
|
||||
xs.tick;
|
||||
|
||||
intfY[2].tick;
|
||||
intfY[1].tick;
|
||||
intfY[0].tick;
|
||||
|
||||
ya2.tick;
|
||||
ya1.tick;
|
||||
ya0.tick;
|
||||
|
||||
yb20.tick;
|
||||
yb21.tick;
|
||||
yb22.tick;
|
||||
yb11.tick;
|
||||
yb00.tick;
|
||||
ybf.tick;
|
||||
|
||||
ys.tick;
|
||||
endtask
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
module top;
|
||||
reg inp;
|
||||
|
||||
initial begin
|
||||
$display("Hello I'm Interface!");
|
||||
$display("Hello I'm Interface!");
|
||||
$display("Hello I'm Interface!");
|
||||
|
||||
$display("Hello I'm ModuleA 0!");
|
||||
$display("Hello I'm ModuleA 1!");
|
||||
$display("Hello I'm ModuleA 1!");
|
||||
|
||||
$display("Hello I'm ModuleB 3!");
|
||||
$display("Hello I'm ModuleB 2!");
|
||||
$display("Hello I'm ModuleB 1!");
|
||||
$display("Hello I'm ModuleB 1!");
|
||||
$display("Hello I'm ModuleB 1!");
|
||||
$display("Hello I'm ModuleB 3!");
|
||||
|
||||
$display("Hello I'm ModuleASet 1 1 0!");
|
||||
|
||||
$display("Hello I'm Interface!");
|
||||
$display("Hello I'm Interface!");
|
||||
$display("Hello I'm Interface!");
|
||||
|
||||
$display("Hello I'm ModuleA 0!");
|
||||
$display("Hello I'm ModuleA 1!");
|
||||
$display("Hello I'm ModuleA 1!");
|
||||
|
||||
$display("Hello I'm ModuleB 3!");
|
||||
$display("Hello I'm ModuleB 2!");
|
||||
$display("Hello I'm ModuleB 1!");
|
||||
$display("Hello I'm ModuleB 1!");
|
||||
$display("Hello I'm ModuleB 1!");
|
||||
$display("Hello I'm ModuleB 3!");
|
||||
|
||||
$display("Hello I'm ModuleCSet 0 0 1!");
|
||||
|
||||
inp = 0; tick;
|
||||
inp = 1; tick;
|
||||
inp = 0; tick;
|
||||
inp = 1; tick;
|
||||
end
|
||||
|
||||
task tick; begin
|
||||
#1;
|
||||
|
||||
$display("I i = %b, v = %b, o = %b", inp, inp, inp ^ 1'b1);
|
||||
$display("I i = %b, v = %b, o = %b", inp, inp ^ 1'b1, inp ^ 1'b1);
|
||||
$display("I i = %b, v = %b, o = %b", inp, inp ^ 1'b1, inp);
|
||||
|
||||
$display("A i.v = %b", inp);
|
||||
$display("A i.v = %b", inp ^ 1'b1);
|
||||
$display("A i.v = %b", inp ^ 1'b1);
|
||||
|
||||
$display("B i_concat = %b, v_concat = %b", {3 {inp}}, {inp, inp ^ 1'b1, inp ^ 1'b1});
|
||||
$display("BN i_concat = %b, v_concat = %b", {3 {inp}}, {inp, inp ^ 1'b1, inp ^ 1'b1});
|
||||
$display("B i_concat = %b, v_concat = %b", {2 {inp}}, {inp, inp ^ 1'b1});
|
||||
$display("BN i_concat = %b, v_concat = %b", {2 {inp}}, {inp, inp ^ 1'b1});
|
||||
$display("B i_concat = %b, v_concat = %b", {1 {inp}}, inp);
|
||||
$display("BN i_concat = %b, v_concat = %b", {1 {inp}}, inp);
|
||||
$display("B i_concat = %b, v_concat = %b", {1 {inp}}, inp ^ 1'b1);
|
||||
$display("BN i_concat = %b, v_concat = %b", {1 {inp}}, inp ^ 1'b1);
|
||||
$display("B i_concat = %b, v_concat = %b", {1 {inp}}, inp ^ 1'b1);
|
||||
$display("BN i_concat = %b, v_concat = %b", {1 {inp}}, inp ^ 1'b1);
|
||||
$display("B i_concat = %b, v_concat = %b", {3 {inp}}, {inp, inp ^ 1'b1, inp ^ 1'b1});
|
||||
$display("BN i_concat = %b, v_concat = %b", {3 {inp}}, {inp, inp ^ 1'b1, inp ^ 1'b1});
|
||||
|
||||
$display("AS i.v = %b", inp ^ 1'b1);
|
||||
$display("AS i.v = %b", inp ^ 1'b1);
|
||||
$display("AS i.v = %b", inp);
|
||||
|
||||
$display("I i = %b, v = %b, o = %b", inp, inp ^ 1'b1, inp);
|
||||
$display("I i = %b, v = %b, o = %b", inp, inp, inp);
|
||||
$display("I i = %b, v = %b, o = %b", inp, inp, inp ^ 1'b1);
|
||||
|
||||
$display("A i.v = %b", inp ^ 1'b1);
|
||||
$display("A i.v = %b", inp);
|
||||
$display("A i.v = %b", inp);
|
||||
|
||||
$display("B i_concat = %b, v_concat = %b", {3 {~inp}}, {inp ^ 1'b1, inp, inp});
|
||||
$display("BN i_concat = %b, v_concat = %b", {3 {~inp}}, {inp ^ 1'b1, inp, inp});
|
||||
$display("B i_concat = %b, v_concat = %b", {2 {~inp}}, {inp ^ 1'b1, inp});
|
||||
$display("BN i_concat = %b, v_concat = %b", {2 {~inp}}, {inp ^ 1'b1, inp});
|
||||
$display("B i_concat = %b, v_concat = %b", {1 {~inp}}, inp ^ 1'b1);
|
||||
$display("BN i_concat = %b, v_concat = %b", {1 {~inp}}, inp ^ 1'b1);
|
||||
$display("B i_concat = %b, v_concat = %b", {1 {~inp}}, inp);
|
||||
$display("BN i_concat = %b, v_concat = %b", {1 {~inp}}, inp);
|
||||
$display("B i_concat = %b, v_concat = %b", {1 {~inp}}, inp);
|
||||
$display("BN i_concat = %b, v_concat = %b", {1 {~inp}}, inp);
|
||||
$display("B i_concat = %b, v_concat = %b", {3 {~inp}}, {inp ^ 1'b1, inp, inp});
|
||||
$display("BN i_concat = %b, v_concat = %b", {3 {~inp}}, {inp ^ 1'b1, inp, inp});
|
||||
|
||||
$display("CS i.v = %b", inp);
|
||||
$display("CS i.v = %b", inp);
|
||||
$display("CS i.v = %b", inp ^ 1'b1);
|
||||
end
|
||||
endtask
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
interface Interface;
|
||||
logic x;
|
||||
endinterface
|
||||
|
||||
module top;
|
||||
Interface intfs[3:2][8:5]();
|
||||
for (genvar x = 2; x <= 3; x = x + 1)
|
||||
for (genvar y = 5; y <= 8; y = y + 1)
|
||||
assign intfs[x][y].x = '1;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
module top;
|
||||
generate
|
||||
if (1) begin : block
|
||||
wire [3:2][8:5] xs;
|
||||
genvar x, y;
|
||||
for (x = 2; x <= 3; x = x + 1)
|
||||
for (y = 5; y <= 8; y = y + 1)
|
||||
assign xs[x][y] = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
`define SHADOW \
|
||||
integer i; \
|
||||
Interface intfs[1:0]();
|
||||
|
||||
interface Interface;
|
||||
integer x;
|
||||
modport ModportA(input .x(x + 1));
|
||||
modport ModportB(input .x(x + 2));
|
||||
endinterface
|
||||
|
||||
module ModuleA(intf);
|
||||
Interface intf;
|
||||
`SHADOW
|
||||
initial #1 $display("ModuleA got %0d", intf.x);
|
||||
ModuleN n(intf);
|
||||
endmodule
|
||||
|
||||
module ModuleB(intf);
|
||||
Interface.ModportA intf;
|
||||
`SHADOW
|
||||
initial #1 $display("ModuleB got %0d", intf.x);
|
||||
ModuleN n(intf);
|
||||
endmodule
|
||||
|
||||
module ModuleC(intf);
|
||||
Interface.ModportB intf;
|
||||
`SHADOW
|
||||
initial #1 $display("ModuleC got %0d", intf.x);
|
||||
ModuleN n(intf);
|
||||
endmodule
|
||||
|
||||
module ModuleN(intf);
|
||||
Interface intf;
|
||||
`SHADOW
|
||||
initial #1 $display("ModuleN got %0d", intf.x);
|
||||
endmodule
|
||||
|
||||
module top;
|
||||
Interface intfs[4:8]();
|
||||
`define LOOP for (genvar i = 4; i <= 8; ++i)
|
||||
`LOOP initial intfs[i].x = i ** 2;
|
||||
`LOOP ModuleA a1(intfs[i]);
|
||||
`LOOP ModuleA a2(intfs[i].ModportA);
|
||||
`LOOP ModuleA a3(intfs[i].ModportB);
|
||||
`LOOP ModuleB b1(intfs[i]);
|
||||
`LOOP ModuleB b2(intfs[i].ModportA);
|
||||
`LOOP ModuleC c1(intfs[i]);
|
||||
`LOOP ModuleC c2(intfs[i].ModportB);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
module top;
|
||||
genvar i;
|
||||
generate
|
||||
|
||||
initial #1;
|
||||
|
||||
`define PRINT(X, offset) \
|
||||
for (i = 4; i <= 8; i = i + 1) \
|
||||
initial begin \
|
||||
$display(`"Module``X got %0d`", i ** 2 + offset); \
|
||||
$display("ModuleN got %0d", i ** 2 + offset); \
|
||||
end
|
||||
|
||||
`PRINT(A, 0)
|
||||
`PRINT(A, 1)
|
||||
`PRINT(A, 2)
|
||||
|
||||
`PRINT(B, 1)
|
||||
`PRINT(B, 1)
|
||||
|
||||
`PRINT(C, 2)
|
||||
`PRINT(C, 2)
|
||||
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
interface Interface;
|
||||
logic x;
|
||||
endinterface
|
||||
|
||||
module Module(intfs);
|
||||
parameter LEFT = 0;
|
||||
parameter RIGHT = 0;
|
||||
Interface intfs[LEFT:RIGHT];
|
||||
logic [LEFT:RIGHT] xs;
|
||||
localparam LO = LEFT > RIGHT ? RIGHT : LEFT;
|
||||
localparam HI = LEFT > RIGHT ? LEFT : RIGHT;
|
||||
for (genvar i = LO; i <= HI; i = i + 1) begin
|
||||
// intentional shadowing of dimension constants
|
||||
localparam LEFT = 0;
|
||||
localparam RIGHT = 0;
|
||||
assign xs[i] = intfs[i].x;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module Instance();
|
||||
parameter LEFT = 0;
|
||||
parameter RIGHT = 0;
|
||||
|
||||
parameter INNER_LEFT = 0;
|
||||
parameter INNER_RIGHT = 0;
|
||||
parameter INNER_OFFSET = 0;
|
||||
|
||||
reg [LEFT:RIGHT] xs;
|
||||
|
||||
localparam DIR = LEFT >= RIGHT ? -1 : 1;
|
||||
Interface intfs[LEFT:RIGHT]();
|
||||
generate
|
||||
genvar i;
|
||||
for (i = LEFT; i <= RIGHT; i = i + DIR)
|
||||
assign intfs[i].x = xs[i];
|
||||
endgenerate
|
||||
|
||||
// intentional name collision with localparams in the module
|
||||
localparam LO = INNER_LEFT >= INNER_RIGHT ? INNER_RIGHT : INNER_LEFT;
|
||||
localparam HI = INNER_LEFT >= INNER_RIGHT ? INNER_LEFT : INNER_RIGHT;
|
||||
localparam LEN = HI - LO + 1;
|
||||
|
||||
Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
|
||||
l(intfs[INNER_LEFT:INNER_RIGHT]);
|
||||
Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
|
||||
m(intfs[LO+:LEN]);
|
||||
Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
|
||||
n(intfs[HI-:LEN]);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
module Module(xs);
|
||||
parameter LEFT = 0;
|
||||
parameter RIGHT = 0;
|
||||
input wire [LEFT:RIGHT] xs;
|
||||
endmodule
|
||||
|
||||
module Instance();
|
||||
parameter LEFT = 0;
|
||||
parameter RIGHT = 0;
|
||||
|
||||
parameter INNER_LEFT = 0;
|
||||
parameter INNER_RIGHT = 0;
|
||||
parameter INNER_OFFSET = 0;
|
||||
|
||||
reg [LEFT:RIGHT] xs;
|
||||
|
||||
localparam LO = INNER_LEFT >= INNER_RIGHT ? INNER_RIGHT : INNER_LEFT;
|
||||
localparam HI = INNER_LEFT >= INNER_RIGHT ? INNER_LEFT : INNER_RIGHT;
|
||||
localparam LEN = HI - LO + 1;
|
||||
|
||||
Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
|
||||
l(xs[INNER_LEFT:INNER_RIGHT]);
|
||||
Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
|
||||
m(xs[LO+:LEN]);
|
||||
Module #(INNER_LEFT + INNER_OFFSET, INNER_RIGHT + INNER_OFFSET)
|
||||
n(xs[HI-:LEN]);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
module Test();
|
||||
parameter BASE = 0;
|
||||
parameter SIZE = 0;
|
||||
parameter DIR = 0;
|
||||
|
||||
localparam LEFT = BASE;
|
||||
localparam RIGHT = BASE + DIR * (SIZE - 1);
|
||||
|
||||
genvar left, right, offset;
|
||||
generate
|
||||
for (left = LEFT + SIZE; left <= RIGHT + SIZE; left = left + 1)
|
||||
for (right = LEFT + SIZE; right <= RIGHT + SIZE; right = right + 1)
|
||||
if ((left - right) * DIR <= 0)
|
||||
for (offset = -2 + SIZE; offset <= 2 + SIZE; offset = offset + 1)
|
||||
begin
|
||||
|
||||
Instance #(
|
||||
LEFT, RIGHT,
|
||||
left - SIZE, right - SIZE, offset - SIZE
|
||||
) i();
|
||||
|
||||
initial begin
|
||||
i.xs = 1;
|
||||
while (i.xs != 0) begin
|
||||
#1;
|
||||
$display("LEFT=%2d RIGHT=%2d INNER_LEFT=%2d INNER_RIGHT=%2d INNER_OFFSET=%2d i.xs=%b i.l.xs=%b i.m.xs=%b i.n.xs=%b",
|
||||
LEFT, RIGHT,
|
||||
left - SIZE, right - SIZE, offset - SIZE,
|
||||
i.xs, i.l.xs, i.m.xs, i.n.xs);
|
||||
i.xs = i.xs + 1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module Suite();
|
||||
parameter SIZE = 0;
|
||||
genvar base;
|
||||
generate
|
||||
for (base = -2 + SIZE; base <= 2 + SIZE; base = base + 1) begin
|
||||
Test #(base - SIZE, SIZE, -1) b();
|
||||
Test #(base - SIZE, SIZE, 1) f();
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module top;
|
||||
Suite #(2) s2();
|
||||
Suite #(3) s3();
|
||||
Suite #(4) s4();
|
||||
endmodule
|
||||
Loading…
Reference in New Issue