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sv2v/test/error/module_param_mismatch_expr.sv

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Systemverilog
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2024-12-15 00:42:13 -05:00
// pattern: parameter "P" in instance "mod" of module "Module" expects an expression, but was given type logic
2021-05-31 14:13:49 -04:00
module Module;
parameter P = 0;
logic [P-1:0] x;
endmodule
module top;
Module #(logic) mod();
endmodule