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9 lines
227 B
Systemverilog
9 lines
227 B
Systemverilog
// pattern: parameter "P" in instance "mod" of module "Module" expects an expression, but was given type logic
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module Module;
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parameter P = 0;
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logic [P-1:0] x;
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endmodule
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module top;
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Module #(logic) mod();
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endmodule
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