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sv2v/test/error/interface_param_mismatch_expr.sv

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Systemverilog
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2024-12-15 00:42:13 -05:00
// pattern: parameter "P" in instance "intf" of interface "Interface" expects an expression, but was given type logic
interface Interface;
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parameter P = 0;
logic [P-1:0] x;
endinterface
module top;
Interface #(logic) intf();
endmodule