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9 lines
247 B
Systemverilog
9 lines
247 B
Systemverilog
// pattern: parameter "P" in instance "intf" of interface "Interface" expects an expression, but was given type logic
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interface Interface;
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parameter P = 0;
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logic [P-1:0] x;
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endinterface
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module top;
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Interface #(logic) intf();
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endmodule
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