test/core/const.v

module top;
    integer w = 11;
    reg [63:0] x = { 32'd11, 32'd12 };
    initial $display("%b %b %b %b", w, x, x[32+:32], x[0+:32]);
endmodule
support const declarations of alias types 2021-02-23 16:45:53 -05:00			`module top;`
			`integer w = 11;`
convert logics with initial values to regs, not wires 2021-07-01 23:17:08 -04:00			`reg [63:0] x = { 32'd11, 32'd12 };`
support const declarations of alias types 2021-02-23 16:45:53 -05:00			`initial $display("%b %b %b %b", w, x, x[32+:32], x[0+:32]);`
			`endmodule`