support const declarations of alias types

src/Language/SystemVerilog/Parser/Parse.y

@@ -454,6 +454,10 @@ TypeAlias :: { Type }
   :                               Identifier Dimensions { Alias   $1       $2 }
   | Identifier               "::" Identifier Dimensions { PSAlias $1    $3 $4 }
   | Identifier ParamBindings "::" Identifier Dimensions { CSAlias $1 $2 $4 $5 }
+PartialTypeAlias :: { Signing -> [Range] -> Type }
+  :                               Identifier { \Unspecified -> Alias   $1       }
+  | Identifier               "::" Identifier { \Unspecified -> PSAlias $1    $3 }
+  | Identifier ParamBindings "::" Identifier { \Unspecified -> CSAlias $1 $2 $4 }
 TypeNonIdent :: { Type }
   : PartialType OptSigning Dimensions { $1 $2 $3 }
   | "type" "(" Expr ")" { TypeOf $3 }
@@ -636,6 +640,7 @@ DeclToken :: { DeclToken }
   | Signing                            {% posInject \p -> DTSigning  p $1 }
   | ExplicitLifetime                   {% posInject \p -> DTLifetime p $1 }
   | "const" PartialType                {% posInject \p -> DTType     p $2 }
+  | "const" PartialTypeAlias           {% posInject \p -> DTType     p $2 }
   | "{" StreamOp StreamSize Concat "}" {% posInject \p -> DTStream   p $2 $3           (map toLHS $4) }
   | "{" StreamOp            Concat "}" {% posInject \p -> DTStream   p $2 (RawNum 1) (map toLHS $3) }
   | opt("var") "type" "(" Expr ")"     {% posInject \p -> DTType     p (\Unspecified -> \[] -> TypeOf $4) }

test/basic/const.sv

@@ -0,0 +1,10 @@
+module top;
+    typedef struct packed { integer y, z; } T;
+    // TODO iverilog doesn't allow references to variables in initializers
+    // if (1) begin : blk
+    // integer a = 11;
+    // integer b = 12;
+    const integer w = 11;
+    const T x = '{ y: 11, z: 12 };
+    initial $display("%b %b %b %b", w, x, x.y, x.z);
+endmodule

test/basic/const.v

@@ -0,0 +1,5 @@
+module top;
+    integer w = 11;
+    wire [63:0] x = { 32'd11, 32'd12 };
+    initial $display("%b %b %b %b", w, x, x[32+:32], x[0+:32]);
+endmodule