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History

John McMaster 24c80d9a62 my_RAM64X1D_2 rename for consistency Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>		2017-12-20 22:46:39 +01:00
..
.gitignore	clb_ram: NDI1MUX tests. Need to split out into dedicated test...	2017-12-20 22:46:39 +01:00
Makefile	clb_ram: WIP before cleanup	2017-12-20 22:46:39 +01:00
README.txt	clb_ram: WIP before cleanup	2017-12-20 22:46:39 +01:00
runme.sh	clb_ram: NDI1MUX tests. Need to split out into dedicated test...	2017-12-20 22:46:39 +01:00
runme.tcl	clb_ram: more testing	2017-12-20 22:46:39 +01:00
top.v	my_RAM64X1D_2 rename for consistency	2017-12-20 22:46:39 +01:00

README.txt

SLICEM RAM test
LUT6 => 64 bits
Focus on 64 bit
32 probably uses same O5/O6 stuff
128 probably uses same MUX stuff
Why isn't there a 256?

RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
RAM128X1S 128-Deep by 1-Wide Random Access Memory (Select RAM)
RAM256X1S 256-Deep by 1-Wide Random Access Memory (Select RAM)
RAM32M 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
RAM32X1S 32-Deep by 1-Wide Static Synchronous RAM
RAM32X1S_1 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
RAM32X2S 32-Deep by 2-Wide Static Synchronous RAM

RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock