mirror of https://github.com/openXC7/prjxray.git
clb_ram: NDI1MUX tests. Need to split out into dedicated test...
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
593d89f36a
commit
a2d7149d30
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@ -0,0 +1,8 @@
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/design.txt
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@ -5,3 +5,5 @@ set -ex
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vivado -mode batch -source runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
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test -z $(fgrep CRITICAL vivado.log)
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@ -1,8 +1,15 @@
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/*
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RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
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RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
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RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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SLICEM at the following:
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SLICE_XxY*
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Where Y any value
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x
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Always even (ie 100, 102, 104, etc)
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In our ROI
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x = 6, 8, 10, 12, 14
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SRL16E: LOC + BEL
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SRLC32E: LOC + BEL
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RAM64X1S: LOCs but doesn't BEL
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*/
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module top(input clk, stb, di, output do);
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@ -34,69 +41,205 @@ module top(input clk, stb, di, output do);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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//ok
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my_NDI1MUX_NMC31 #(.LOC("SLICE_X6Y100"))
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my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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/*
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my_RAM64M #(.LOC("SLICE_X6Y100"))
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my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X6Y101"))
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my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_RAM64X1S_1 #(.LOC("SLICE_X6Y102"))
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my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_RAM64X2S #(.LOC("SLICE_X6Y103"))
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my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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my_RAM64X1D #(.LOC("SLICE_X6Y104"))
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my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_RAM128X1D #(.LOC("SLICE_X6Y105"))
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my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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*/
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/*
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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my_BDI1MUX_AI(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_BDI1MUX_BDI1 #(.LOC("SLICE_X6Y101"), .BELO("B6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BDI1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_BDI1MUX_BMC31 #(.LOC("SLICE_X6Y102"), .BELO("B6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BMC31(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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*/
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/*
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//BEL isn't taking effect
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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//Can't find a valid solution
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my_NDI1MUX_NDI1 #(.LOC("SLICE_X6Y101"))
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my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8]));
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*/
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my_NDI1MUX_NI #(.LOC("SLICE_X6Y102"))
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my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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/*
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//BEL works
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//No unknown bits
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my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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//ok
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my_BDI1MUX_AI #(.LOC("SLICE_X8Y100"), .BEL("A6LUT"))
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my_BDI1MUX_AI(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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*/
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/*
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//bad
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my_BDI1MUX_BDI1 #(.LOC("SLICE_X8Y101"), .BELO("C6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BDI1(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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*/
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/*
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//ok
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my_BDI1MUX_BMC31 #(.LOC("SLICE_X8Y102"), .BELO("B6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BMC31(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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*/
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//BEL works
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my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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endmodule
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module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
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/****************************************************************************
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Tries to set all three muxes at once
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****************************************************************************/
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module my_NDI1MUX_NMC31 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "SLICE_X6Y100";
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wire [3:0] q31;
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(* LOC=LOC, BEL="D6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[0]),
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.Q31(q31[3]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="C6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[1]),
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.Q31(q31[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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//.D(din[7]));
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.D(q31[3]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[2]),
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.Q31(q31[1]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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//.D(din[7]));
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.D(q31[2]));
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[3]),
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.Q31(q31[0]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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//.D(din[7]));
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.D(q31[1]));
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endmodule
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/*
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//Cannot loc instance 'roi/my_NDI1MUX_NDI1/lutc' at site SLICE_X6Y100,
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//Bel does not match with the valid locations at which this inst can be placed
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module my_NDI1MUX_NDI1 (input clk, input [31:0] din, output [7:0] dout);
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parameter LOC = "SLICE_X6Y100";
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wire [3:0] q31;
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(* LOC=LOC, BEL="D6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[0]),
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.Q31(q31[3]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="C6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[1]),
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.Q31(q31[2]),
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.A(din[12:8]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[15]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[2]),
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.Q31(q31[1]),
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.A(din[20:16]),
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.CE(din[5]),
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.CLK(din[6]),
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//.D(din[23]));
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.D(q31[2]));
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[3]),
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.Q31(q31[0]),
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.A(din[28:24]),
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.CE(din[5]),
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.CLK(din[6]),
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//.D(din[31]));
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.D(q31[2]));
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endmodule
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*/
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module my_NDI1MUX_NI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "SLICE_X6Y100";
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(* LOC=LOC, BEL="D6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[0]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="C6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[1]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[2]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[3]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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endmodule
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/****************************************************************************
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Individual mux tests
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****************************************************************************/
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module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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@ -115,89 +258,13 @@ module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
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.D(din[7]));
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endmodule
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module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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SRL16E #(
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) SRL16E (
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.Q(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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RAM64X1S #(
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) RAM64X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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//bad
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//Ended in D6LUT and A6LUT
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/*
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module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="B6LUT";
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parameter BELI="A6LUT";
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wire da = din[6];
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(* LOC=LOC, BEL=BELO *)
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RAM64X1S #(
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) lutb (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(da),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC, BEL=BELI *)
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RAM64X1S #(
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) luta (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(da),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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*/
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//Lets try CMC31 chaining instead
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module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="C6LUT";
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parameter BELI="A6LUT";
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wire da = din[6];
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wire mc31c;
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//wire da = din[6];
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(* LOC=LOC, BEL=BELO *)
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SRLC32E #(
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@ -220,7 +287,7 @@ module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(da));
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.D(mc31c));
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endmodule
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//ok
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@ -258,6 +325,87 @@ endmodule
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/*
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Old stuff
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This is original file, move mux test out and restore this
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*/
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||||
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||||
|
||||
|
||||
/*
|
||||
//BEL works
|
||||
my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
|
||||
c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
|
||||
my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
|
||||
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
|
||||
my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
|
||||
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
|
||||
my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
|
||||
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
|
||||
*/
|
||||
|
||||
module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
parameter BEL="A6LUT";
|
||||
|
||||
wire mc31c;
|
||||
|
||||
(* LOC=LOC, BEL=BEL *)
|
||||
SRLC32E #(
|
||||
.INIT(32'h00000000),
|
||||
.IS_CLK_INVERTED(1'b0)
|
||||
) lut (
|
||||
.Q(dout[0]),
|
||||
.Q31(mc31c),
|
||||
.A(din[4:0]),
|
||||
.CE(din[5]),
|
||||
.CLK(din[6]),
|
||||
.D(din[7]));
|
||||
endmodule
|
||||
|
||||
/*
|
||||
//BEL works
|
||||
//No unknown bits
|
||||
my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
|
||||
c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
|
||||
my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
|
||||
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
|
||||
my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
|
||||
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
|
||||
my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
|
||||
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
|
||||
*/
|
||||
|
||||
module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
parameter BEL="A6LUT";
|
||||
|
||||
(* LOC=LOC, BEL=BEL *)
|
||||
SRL16E #(
|
||||
) SRL16E (
|
||||
.Q(dout[0]),
|
||||
.A0(din[0]),
|
||||
.A1(din[1]),
|
||||
.A2(din[2]),
|
||||
.A3(din[3]),
|
||||
.CE(din[4]),
|
||||
.CLK(din[5]),
|
||||
.D(din[6]));
|
||||
endmodule
|
||||
|
||||
module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
parameter BEL="A6LUT";
|
||||
|
|
@ -282,6 +430,27 @@ module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
|
|||
endmodule
|
||||
|
||||
|
||||
/*
|
||||
RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
|
||||
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
|
||||
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
|
||||
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
|
||||
*/
|
||||
|
||||
/*
|
||||
my_RAM64M #(.LOC("SLICE_X6Y100"))
|
||||
my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
|
||||
my_RAM64X1S #(.LOC("SLICE_X6Y101"))
|
||||
my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
|
||||
my_RAM64X1S_1 #(.LOC("SLICE_X6Y102"))
|
||||
my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
|
||||
my_RAM64X2S #(.LOC("SLICE_X6Y103"))
|
||||
my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
|
||||
my_RAM64X1D #(.LOC("SLICE_X6Y104"))
|
||||
my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
|
||||
my_RAM128X1D #(.LOC("SLICE_X6Y105"))
|
||||
my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
|
||||
*/
|
||||
|
||||
module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
|
|
|
|||
Loading…
Reference in New Issue