mirror of https://github.com/openXC7/prjxray.git
clb_ram: WIP before cleanup
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
bd517837bc
commit
593d89f36a
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@ -0,0 +1,27 @@
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N := 3
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all:
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bash runme.sh
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test -z $(fgrep CRITICAL vivado.log)
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${XRAY_SEGPRINT} -z -D design.bits >design.txt
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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.PHONY: database pushdb clean
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@ -0,0 +1,22 @@
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SLICEM RAM test
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LUT6 => 64 bits
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Focus on 64 bit
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32 probably uses same O5/O6 stuff
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128 probably uses same MUX stuff
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Why isn't there a 256?
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RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
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RAM128X1S 128-Deep by 1-Wide Random Access Memory (Select RAM)
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RAM256X1S 256-Deep by 1-Wide Random Access Memory (Select RAM)
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RAM32M 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
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RAM32X1S 32-Deep by 1-Wide Static Synchronous RAM
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RAM32X1S_1 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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RAM32X2S 32-Deep by 2-Wide Static Synchronous RAM
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RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
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RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
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RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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@ -0,0 +1,7 @@
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#!/bin/bash
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set -ex
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# rm -f vivado*.log vivado*.jou
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vivado -mode batch -source runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
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@ -0,0 +1,29 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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# Need to go outside
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# SLICE_X12Y100:SLICE_X27Y149
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# resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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resize_pblock [get_pblocks roi] -add "SLICE_X6Y100:SLICE_X27Y149"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,385 @@
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/*
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RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
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RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
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RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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*/
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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/*
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my_RAM64M #(.LOC("SLICE_X6Y100"))
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my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X6Y101"))
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my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_RAM64X1S_1 #(.LOC("SLICE_X6Y102"))
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my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_RAM64X2S #(.LOC("SLICE_X6Y103"))
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my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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my_RAM64X1D #(.LOC("SLICE_X6Y104"))
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my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_RAM128X1D #(.LOC("SLICE_X6Y105"))
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my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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*/
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/*
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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my_BDI1MUX_AI(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_BDI1MUX_BDI1 #(.LOC("SLICE_X6Y101"), .BELO("B6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BDI1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_BDI1MUX_BMC31 #(.LOC("SLICE_X6Y102"), .BELO("B6LUT"), .BELI("A6LUT"))
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my_BDI1MUX_BMC31(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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*/
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/*
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//BEL isn't taking effect
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_BDI1MUX_AI #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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*/
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/*
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//BEL works
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//No unknown bits
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my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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*/
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//BEL works
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my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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endmodule
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module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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wire mc31c;
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(* LOC=LOC, BEL=BEL *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lut (
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.Q(dout[0]),
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.Q31(mc31c),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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endmodule
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module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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SRL16E #(
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) SRL16E (
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.Q(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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RAM64X1S #(
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) RAM64X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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//bad
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//Ended in D6LUT and A6LUT
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/*
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module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="B6LUT";
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parameter BELI="A6LUT";
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wire da = din[6];
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(* LOC=LOC, BEL=BELO *)
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RAM64X1S #(
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) lutb (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(da),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC, BEL=BELI *)
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RAM64X1S #(
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) luta (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(da),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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*/
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//Lets try CMC31 chaining instead
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module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="C6LUT";
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parameter BELI="A6LUT";
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wire da = din[6];
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(* LOC=LOC, BEL=BELO *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[0]),
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.Q31(mc31c),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL=BELI *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[1]),
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.Q31(dout[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(da));
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endmodule
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//ok
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module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="B6LUT";
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parameter BELI="A6LUT";
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wire mc31b;
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(* LOC=LOC, BEL=BELO *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[0]),
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.Q31(mc31b),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL=BELI *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[1]),
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.Q31(dout[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(mc31b));
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endmodule
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module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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RAM64M #(
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) RAM64M (
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.DOA(dout[0]),
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.DOB(dout[1]),
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.DOC(dout[2]),
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.DOD(dout[3]),
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.ADDRA(din[0]),
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.ADDRB(din[1]),
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.ADDRC(din[2]),
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.ADDRD(din[3]),
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.DIA(din[4]),
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.DIB(din[5]),
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.DIC(din[6]),
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.DID(din[7]),
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.WCLK(clk),
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.WE(din[1]));
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endmodule
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module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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RAM64X1S #(
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) RAM64X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1S_1 #(
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) RAM64X1S_1 (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X2S #(
|
||||
) RAM64X2S (
|
||||
.O0(dout[0]),
|
||||
.O1(dout[1]),
|
||||
.A0(din[0]),
|
||||
.A1(din[1]),
|
||||
.A2(din[2]),
|
||||
.A3(din[3]),
|
||||
.A4(din[4]),
|
||||
.A5(din[5]),
|
||||
.D0(din[6]),
|
||||
.D1(din[7]),
|
||||
.WCLK(clk),
|
||||
.WE(din[1]));
|
||||
endmodule
|
||||
|
||||
module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
|
||||
(* LOC=LOC *)
|
||||
RAM64X1D #(
|
||||
.INIT(64'h0),
|
||||
.IS_WCLK_INVERTED(1'b0)
|
||||
) RAM64X1D (
|
||||
.DPO(dout[0]),
|
||||
.D(din[0]),
|
||||
.WCLK(clk),
|
||||
.WE(din[2]),
|
||||
.A0(din[3]),
|
||||
.A1(din[4]),
|
||||
.A2(din[5]),
|
||||
.A3(din[6]),
|
||||
.A4(din[7]),
|
||||
.A5(din[0]),
|
||||
.DPRA0(din[1]),
|
||||
.DPRA1(din[2]),
|
||||
.DPRA2(din[3]),
|
||||
.DPRA3(din[4]),
|
||||
.DPRA4(din[5]),
|
||||
.DPRA5(din[6]));
|
||||
endmodule
|
||||
|
||||
module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
|
||||
(* LOC=LOC *)
|
||||
RAM128X1D #(
|
||||
.INIT(128'h0),
|
||||
.IS_WCLK_INVERTED(1'b0)
|
||||
) RAM128X1D (
|
||||
.DPO(dout[0]),
|
||||
.SPO(dout[1]),
|
||||
.D(din[0]),
|
||||
.WCLK(clk),
|
||||
.WE(din[2]));
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue