History

Davide 73b1e27f78 Added tags for headers, subheaders and structured README files a bit Signed-off-by: Davide <davide.toldo@stud.tu-darmstadt.de>		2018-02-14 12:24:18 +01:00
..
.gitignore	clb_ram: NDI1MUX tests. Need to split out into dedicated test...	2017-12-20 22:46:39 +01:00
Makefile	minitests: centralize common case, cleanup Makefile/runme.sh relation, delete fuzzer artifacts	2017-12-22 13:36:58 -08:00
README.md	Added tags for headers, subheaders and structured README files a bit	2018-02-14 12:24:18 +01:00
top.v	clb_ram minitest delete dead code	2017-12-20 23:28:33 +01:00

README.md

CLB_RAM Minitest

Purpose

SLICEM RAM test
LUT6 => 64 bits
Focus on 64 bit
32 probably uses same O5/O6 stuff
128 probably uses same MUX stuff
Why isn't there a 256?

Result

RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
RAM128X1S 128-Deep by 1-Wide Random Access Memory (Select RAM)
RAM256X1S 256-Deep by 1-Wide Random Access Memory (Select RAM)
RAM32M 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
RAM32X1S 32-Deep by 1-Wide Static Synchronous RAM
RAM32X1S_1 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
RAM32X2S 32-Deep by 2-Wide Static Synchronous RAM

RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock