mirror of https://github.com/openXC7/prjxray.git
clb_ram minitest delete dead code
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
5c4c5097d4
commit
9d519f99b3
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@ -104,75 +104,6 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
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endmodule
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module roi_asdfsdf(input clk, input [255:0] din, output [255:0] dout);
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//RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
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my_RAM32X1D #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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//RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
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//2LUT
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my_RAM64X1D #(.LOC("SLICE_X12Y101"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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//4LUT
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my_RAM64X1D_2 #(.LOC("SLICE_X12Y102"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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//RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
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my_RAM128X1D #(.LOC("SLICE_X12Y103"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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endmodule
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//Activate W*MUX
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module roi_sdffd(input clk, input [255:0] din, output [255:0] dout);
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/*
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seg SEG_CLBLM_L_X10Y100
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bit 00_40
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bit 01_23
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bit 31_16
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bit 31_17
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bit 31_46
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bit 31_47
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*/
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my_RAM128X1D #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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/*
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seg SEG_CLBLM_L_X10Y102
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bit 00_40
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bit 01_23
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bit 31_46
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bit 31_47
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*/
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my_RAM128X1S #(.LOC("SLICE_X12Y102"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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/*
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seg SEG_CLBLM_L_X10Y103
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bit 00_40
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bit 01_23
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bit 01_27
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bit 31_16
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bit 31_17
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bit 31_46
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bit 31_47
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*/
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my_RAM256X1S #(.LOC("SLICE_X12Y103"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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/*
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seg SEG_CLBLM_L_X10Y104
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bit 00_00
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bit 01_23
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bit 31_16
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bit 31_47
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*/
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/*
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my_RAM64X1S_2 #(.LOC("SLICE_X12Y104"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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*/
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endmodule
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//It created a LUT instead of aggregating using WA7MUX
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module my_RAM64X1S_2_mux (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -208,88 +139,6 @@ module my_RAM64X1S_2_mux (input clk, input [7:0] din, output [7:0] dout);
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.WE(din[0]));
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endmodule
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//Try to get a conflict on memory LUT vs LUT6_2
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module roi_lkjsadfsdf(input clk, input [255:0] din, output [255:0] dout);
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my_multilut #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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endmodule
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/*
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seg SEG_CLBLM_L_X10Y100
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bit 00_24
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bit 01_23
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bit 01_43
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bit 30_17
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bit 30_46
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bit 31_47
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*/
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module my_multilut (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[0]),
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.A2(din[0]),
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.A3(din[0]),
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.A4(din[0]),
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.A5(din[0]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[2]),
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.Q31(),
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.A({din[0], din[0], din[0], din[0], din[0]}),
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.CE(din[0]),
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.CLK(clk),
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.D(din[0]));
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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SRL16E #(
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) lutb (
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.Q(dout[1]),
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.A0(din[0]),
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.A1(din[0]),
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.A2(din[0]),
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.A3(din[0]),
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.CE(din[0]),
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.CLK(clk),
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.D(din[0]));
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_1CE0_0000_0001)
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) luta (
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.I0(din[0]),
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.I1(din[0]),
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.I2(din[0]),
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.I3(din[0]),
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.I4(din[0]),
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.I5(din[0]),
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.O5(),
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.O6(dout[0]));
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endmodule
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//1LUT 4
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module roi_(input clk, input [255:0] din, output [255:0] dout);
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my_SRL16E_4 #(.LOC("SLICE_X12Y100"))
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c7(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRLC32E_4 #(.LOC("SLICE_X12Y101"))
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c3(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_RAM32X1S_4 #(.LOC("SLICE_X12Y102"))
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c19(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_RAM64X1S_4 #(.LOC("SLICE_X12Y103"))
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c11(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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endmodule
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module my_SRL16E_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -688,364 +537,6 @@ module my_RAM64X1S_4 (input clk, input [7:0] din, output [7:0] dout);
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.WE(din[0]));
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endmodule
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//1LUT
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module roi_asdf(input clk, input [255:0] din, output [255:0] dout);
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//LOCs
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my_SRLC32E #(.LOC("SLICE_X12Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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//LOCs
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my_SRL16E #(.LOC("SLICE_X12Y107"), .BEL("D6LUT"))
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c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
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//No LOC
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my_RAM64X1S #(.LOC("SLICE_X12Y111"), .BEL("D6LUT"))
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c11(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
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//No LOC
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y115"), .BEL("D6LUT"))
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c15(.clk(clk), .din(din[ 120 +: 8]), .dout(dout[ 120 +: 8]));
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//No LOC
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my_RAM32X1S #(.LOC("SLICE_X12Y119"), .BEL("D6LUT"))
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c19(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8]));
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//No LOC
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y123"), .BEL("D6LUT"))
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c23(.clk(clk), .din(din[ 184 +: 8]), .dout(dout[ 184 +: 8]));
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endmodule
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//1LUT
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module roi_asdsdaf(input clk, input [255:0] din, output [255:0] dout);
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//LOCs
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my_SRLC32E #(.LOC("SLICE_X12Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X12Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X12Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X12Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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//LOCs
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my_SRL16E #(.LOC("SLICE_X12Y104"), .BEL("A6LUT"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_SRL16E #(.LOC("SLICE_X12Y105"), .BEL("B6LUT"))
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c5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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my_SRL16E #(.LOC("SLICE_X12Y106"), .BEL("C6LUT"))
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c6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
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my_SRL16E #(.LOC("SLICE_X12Y107"), .BEL("D6LUT"))
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c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
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//No LOC
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my_RAM64X1S #(.LOC("SLICE_X12Y108"), .BEL("A6LUT"))
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c8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X12Y109"), .BEL("B6LUT"))
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c9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X12Y110"), .BEL("C6LUT"))
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c10(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X12Y111"), .BEL("D6LUT"))
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c11(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
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//No LOC
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y112"), .BEL("A6LUT"))
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c12(.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 96 +: 8]));
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y113"), .BEL("B6LUT"))
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c13(.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 104 +: 8]));
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y114"), .BEL("C6LUT"))
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c14(.clk(clk), .din(din[ 112 +: 8]), .dout(dout[ 112 +: 8]));
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y115"), .BEL("D6LUT"))
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c15(.clk(clk), .din(din[ 120 +: 8]), .dout(dout[ 120 +: 8]));
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//No LOC
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my_RAM32X1S #(.LOC("SLICE_X12Y116"), .BEL("A6LUT"))
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c16(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
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my_RAM32X1S #(.LOC("SLICE_X12Y117"), .BEL("B6LUT"))
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c17(.clk(clk), .din(din[ 136 +: 8]), .dout(dout[ 136 +: 8]));
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my_RAM32X1S #(.LOC("SLICE_X12Y118"), .BEL("C6LUT"))
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c18(.clk(clk), .din(din[ 144 +: 8]), .dout(dout[ 144 +: 8]));
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my_RAM32X1S #(.LOC("SLICE_X12Y119"), .BEL("D6LUT"))
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c19(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8]));
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//No LOC
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y120"), .BEL("A6LUT"))
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c20(.clk(clk), .din(din[ 160 +: 8]), .dout(dout[ 160 +: 8]));
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y121"), .BEL("B6LUT"))
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c21(.clk(clk), .din(din[ 168 +: 8]), .dout(dout[ 168 +: 8]));
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y122"), .BEL("C6LUT"))
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c22(.clk(clk), .din(din[ 176 +: 8]), .dout(dout[ 176 +: 8]));
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y123"), .BEL("D6LUT"))
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c23(.clk(clk), .din(din[ 184 +: 8]), .dout(dout[ 184 +: 8]));
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endmodule
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//One of each
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module roi_one(input clk, input [255:0] din, output [255:0] dout);
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y100
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM64X1D_2 #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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//1LUT
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/*
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seg SEG_CLBLM_L_X10Y101
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bit 00_00
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*/
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my_SRLC32E #(.LOC("SLICE_X12Y101"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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//1LUT
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/*
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No unknown bits
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*/
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my_SRL16E #(.LOC("SLICE_X12Y102"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y103
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bit 00_00
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bit 00_20
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bit 01_43
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM64M #(.LOC("SLICE_X12Y103"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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//1LUT
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/*
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No unknown bits
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*/
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my_RAM64X1S #(.LOC("SLICE_X12Y104"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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//1LUT
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/*
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No unknown bits
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*/
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my_RAM64X1S_1 #(.LOC("SLICE_X12Y105"))
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c5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y106
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bit 01_43
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bit 31_46
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*/
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my_RAM64X2S #(.LOC("SLICE_X12Y106"))
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c6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y107
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bit 31_46
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*/
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my_RAM64X1D #(.LOC("SLICE_X12Y107"))
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c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y108
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bit 00_40
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM128X1D #(.LOC("SLICE_X12Y108"))
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c8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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//4LUT
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/*
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seg SEG_CLBLM_L_X10Y109
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bit 00_00
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bit 00_20
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bit 01_43
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bit 31_16
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bit 31_17
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bit 31_46
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*/
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my_RAM32M #(.LOC("SLICE_X12Y109"))
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c9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y110
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bit 31_46
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*/
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my_RAM32X1D #(.LOC("SLICE_X12Y110"))
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c10(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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//1LUT
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/*
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No bits
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*/
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my_RAM32X1S #(.LOC("SLICE_X12Y111"))
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c11(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
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//1LUT
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/*
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No bits
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*/
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my_RAM32X1S_1 #(.LOC("SLICE_X12Y112"))
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c12(.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 96 +: 8]));
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//2LUT
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/*
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seg SEG_CLBLM_L_X10Y113
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bit 31_46
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*/
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my_RAM32X2S #(.LOC("SLICE_X12Y113"))
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c13(.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 104 +: 8]));
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endmodule
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module roi2(input clk, input [255:0] din, output [255:0] dout);
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/*
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//Test: SRLC32E at each BEL location
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//Takes one LUT
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//BEL works
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my_SRLC32E #(.LOC("SLICE_X12Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X12Y101"), .BEL("B6LUT"))
|
||||
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
|
||||
my_SRLC32E #(.LOC("SLICE_X12Y102"), .BEL("C6LUT"))
|
||||
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
|
||||
my_SRLC32E #(.LOC("SLICE_X12Y103"), .BEL("D6LUT"))
|
||||
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
|
||||
*/
|
||||
|
||||
//BEL works
|
||||
/*
|
||||
01_23: common bit
|
||||
Seems to be set whenever a SLICEM contains a LUT as RAM element
|
||||
|
||||
D
|
||||
01_59
|
||||
30_47
|
||||
C
|
||||
00_28
|
||||
30_46
|
||||
B
|
||||
00_24
|
||||
30_17
|
||||
A
|
||||
00_04
|
||||
30_16
|
||||
|
||||
seg SEG_CLBLM_L_X10Y103
|
||||
bit 01_23
|
||||
bit 01_59
|
||||
bit 30_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y102
|
||||
bit 00_28
|
||||
bit 01_23
|
||||
bit 30_46
|
||||
|
||||
seg SEG_CLBLM_L_X10Y101
|
||||
bit 00_24
|
||||
bit 01_23
|
||||
bit 30_17
|
||||
|
||||
seg SEG_CLBLM_L_X10Y100
|
||||
bit 00_04
|
||||
bit 01_23
|
||||
bit 30_16
|
||||
*/
|
||||
/*
|
||||
my_SRL16E #(.LOC("SLICE_X12Y100"), .BEL("A6LUT"))
|
||||
c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
|
||||
my_SRL16E #(.LOC("SLICE_X12Y101"), .BEL("B6LUT"))
|
||||
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
|
||||
my_SRL16E #(.LOC("SLICE_X12Y102"), .BEL("C6LUT"))
|
||||
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
|
||||
my_SRL16E #(.LOC("SLICE_X12Y103"), .BEL("D6LUT"))
|
||||
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
|
||||
*/
|
||||
|
||||
/*
|
||||
RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
|
||||
RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
|
||||
RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
|
||||
RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
|
||||
*/
|
||||
|
||||
/*
|
||||
seg SEG_CLBLM_L_X10Y127
|
||||
bit 01_23
|
||||
bit 31_16
|
||||
bit 31_17
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y100
|
||||
bit 01_23
|
||||
bit 31_16
|
||||
bit 31_17
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
*/
|
||||
/*
|
||||
my_RAM64X1D_2 #(.LOC("SLICE_X6Y100"))
|
||||
dut0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
|
||||
my_RAM64X1D_2 #(.LOC("SLICE_X6Y127"))
|
||||
dut1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
|
||||
my_RAM64X1D_2 #(.LOC("SLICE_X12Y100"))
|
||||
dut2(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
|
||||
my_RAM64X1D_2 #(.LOC("SLICE_X12Y127"))
|
||||
dut3(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
seg SEG_CLBLM_L_X10Y105
|
||||
bit 00_40
|
||||
bit 01_23
|
||||
bit 31_16
|
||||
bit 31_17
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y104
|
||||
bit 01_23
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y103
|
||||
bit 01_23
|
||||
bit 01_43
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y102
|
||||
bit 01_23
|
||||
bit 31_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y101
|
||||
bit 01_23
|
||||
bit 31_47
|
||||
|
||||
seg SEG_CLBLM_L_X10Y100
|
||||
bit 00_00
|
||||
bit 00_20
|
||||
bit 01_23
|
||||
bit 01_43
|
||||
bit 31_16
|
||||
bit 31_17
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
*/
|
||||
/*
|
||||
my_RAM64M #(.LOC("SLICE_X12Y100"))
|
||||
my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
|
||||
my_RAM64X1S #(.LOC("SLICE_X12Y101"))
|
||||
my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
|
||||
my_RAM64X1S_1 #(.LOC("SLICE_X12Y102"))
|
||||
my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
|
||||
my_RAM64X2S #(.LOC("SLICE_X12Y103"))
|
||||
my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
|
||||
my_RAM64X1D #(.LOC("SLICE_X12Y104"))
|
||||
my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
|
||||
my_RAM128X1D #(.LOC("SLICE_X12Y105"))
|
||||
my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
|
||||
*/
|
||||
endmodule
|
||||
|
||||
module my_RAM64X1D_2 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue