luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/minitests/litex/src.yosys
History
Maciej Kurc 68c810ce3b Added source files dependencies to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 		2019-06-25 10:14:20 +02:00
..
Makefile Added source files dependencies to Makefiles 2019-06-25 10:14:20 +02:00
VexRiscv_Linux.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
mem.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem_1.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
synth.ys Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.tcl Added bitread and segprint to the Makefile flow 2019-06-17 14:52:06 +02:00
top.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.xdc Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00