Tim 'mithro' Ansell 4fbcbb5c87 minitests/litex*: Fix location of clean_json5.py tool. ... Fixes #1255. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>		2020-02-24 23:07:48 -08:00
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Makefile	minitests/litex*: Fix location of clean_json5.py tool.	2020-02-24 23:07:48 -08:00
VexRiscv_Linux.v	MAKE - Format Trailing Whitespace	2019-10-26 10:04:52 +01:00
mem.init	Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board)	2019-06-13 15:58:06 +02:00
mem_1.init	Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board)	2019-06-13 15:58:06 +02:00
missing_bit_report.py	MAKE - Format Trailing Whitespace	2019-10-26 10:04:52 +01:00
synth.ys	Fixed the LiteX generated SoC to be Linux capable	2019-06-17 13:45:11 +02:00
top.tcl	Run make format.	2019-07-23 17:21:26 -07:00
top.v	Fixed the LiteX generated SoC to be Linux capable	2019-06-17 13:45:11 +02:00
top.xdc	Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board)	2019-06-13 15:58:06 +02:00