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prjxray/minitests/litex/src.yosys
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Keith Rothman 6c4e6aa718 Update HCLK_IOI offset to match tilegrid 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 		2019-07-26 17:18:48 -07:00
..
Makefile Filter out non-IOB bits. 2019-07-23 13:38:03 -07:00
VexRiscv_Linux.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
mem.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem_1.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
missing_bit_report.py Update HCLK_IOI offset to match tilegrid 2019-07-26 17:18:48 -07:00
synth.ys Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.tcl Run make format. 2019-07-23 17:21:26 -07:00
top.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.xdc Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00