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prjxray/minitests/litex/src.yosys
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Jake Mercer bf11f43390 FORMAT - Run `make format` 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 		2019-10-22 19:35:24 +01:00
..
Makefile Filter out non-IOB bits. 2019-07-23 13:38:03 -07:00
VexRiscv_Linux.v FORMAT - Run `make format` 2019-10-22 19:35:24 +01:00
mem.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem_1.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
missing_bit_report.py FORMAT - Run `make format` 2019-10-22 19:35:24 +01:00
synth.ys Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.tcl Run make format. 2019-07-23 17:21:26 -07:00
top.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.xdc Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00