mirror of https://github.com/openXC7/prjxray.git
a8de0afdb3
The open-flow (Yosys → nextpnr-xilinx → FASM → bitstream) now produces
silicon-functional bits on VC707 xc7vx485tffg1761-2 for:
- rst_to_led (IBUF↔OBUF passthrough)
- counter_skewfree (button-clocked 8b counter, general routing)
- counter_sw_bufr (button → BUFR → 8b counter)
- counter_bufr (200 MHz LVDS sysclk → IBUFDS → BUFR → 8b counter)
- counter_2bufg (2× BUFGCTRL on the same source)
- vc707_telegraph (125 MHz crystal → IBUFDS_GTE2 → BUFG → UART smoke test)
- vc707_picosoc (picorv32 + simpleuart + BRAM @ 125 MHz; UART prints
'PicoSoC alive on VC707 @ 125 MHz' on /dev/ttyUSB0)
Highlights of this drop:
utils/fasm2frames.py (+223 net):
- Bank-glue auto-injection for HP-bank IOB18 — IBUF/OBUF (Y0+Y1) +
IBUFDS differential pair. Fires off the FASM-level direction
heuristic (.IN/.IN_ONLY/IBUFDISABLE for IBUF, .DRIVE. for OBUF,
.IN_DIFF for IBUFDS; .SLEW. is unreliable as a marker — gets emitted
on default-state IOBs too).
- INT_L_X32Y49 DCI cascade / bank-active markers when any LIOB18_X81
Y1 OBUF is present.
- PUDC_B emission rewritten for HP-bank IOSTANDARDs (10 features
cover Y0 + Y1 default-state; all 9 historic 'PUDC_B glue' bits
flow naturally from the existing IOSTANDARD segbits).
- HCLK_L per-BUFRCLK-channel 'active' marker — currently codified
for BUFRCLK3 (the channel exercised by counter_sw_bufr).
- GFAN T-tie root glue — INT_L_X62Y(N+10).GFAN_TIE_ROOT_GLUE when
INT_L_X62Y(N).GFAN0.GND_WIRE appears (OBUF.T → GND routing).
- PUDC_B tile excluded from the bank-glue walk (its IN features are
virtual; injecting OBUF_HP_BANK_GLUE on it produces spurious bits).
utils/utils.tcl (+47):
- write_pip_txtdata bulk-fetch — replaces per-net foreach pip with
bulk get_pips + bulk get_property IS_DIRECTIONAL + cached
dst_wire_to_num_pips. ~4× speed-up on xc7vx485t (per-spec time on
041-clk-hrow-pips / 045-hclk-cmt-pips drops from ~1.5 h to ~25 min).
utils/mergedb.sh (+15):
- LIOI / LIOI_TBYTESRC / LIOI_TBYTETERM / LIOB18 / mask_liob18 sed
rewrites for the L-side IOI/IOB18 tiles on HP-only parts (xc7vx485t
uses left-side IOB18 too; upstream kintex7 mergedb only knew the
right side).
11 fuzzers patched for virtex7 readiness:
- 030-iob18 Makefile: split DB target for virtex7 (HP-only); the BUFR
HP-bank results come from the actual fuzzer rather than HR-side sed.
- 037-iob18-pips: L-side mirror tiles (LIOI / LIOI_TBYTESRC /
LIOI_TBYTETERM) added to segdata glob; *_SING tiles excluded;
EXCLUDE_RE updated for L-side prefixes.
- 039-hclk-config: split virtex7 vs kintex7 (HCLK_IOI vs HCLK_IOI3);
XRAY_IOSTANDARD env var; IOB18M/IOB33M alternation.
- 047a-hclk-idelayctrl-pips: accepts both HCLK_IOI and HCLK_IOI3.
- 041, 045, 034, 034b, 043, 044, 046: removed local
write_pip_txtdata override that shadowed the patched utils.tcl
bulk-fetch (was re-introducing the slow per-net Tcl path).
README.md (+86):
- 'Virtex-7 Port Status (virtex7-support branch)' section —
achievements, goals, work-in-progress, constraints.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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||
|---|---|---|
| .. | ||
| openocd | ||
| test_data | ||
| .gitignore | ||
| __init__.py | ||
| addrwidth.py | ||
| bit2fasm.py | ||
| blockwidth.py | ||
| checkdb.py | ||
| clean_json5.py | ||
| cleandb.py | ||
| cmp.py | ||
| create_environment.py | ||
| create_timing_worksheet_db.py | ||
| dbfixup.py | ||
| diff_db_bits.py | ||
| diff_db_json.py | ||
| environment.python.sh | ||
| environment.sh | ||
| fasm2frames.py | ||
| fasm2pips.py | ||
| fasm_pprint.py | ||
| find_missing_segbits.py | ||
| genheader.sh | ||
| group.py | ||
| groupmask.py | ||
| info_md.py | ||
| make_ports.py | ||
| makesdf.py | ||
| maskmerge.sh | ||
| maskview.py | ||
| mergedb.py | ||
| mergedb.sh | ||
| parsedb.py | ||
| quick_test.py | ||
| roi_all.py | ||
| sdfmerge.py | ||
| segprint.py | ||
| segview.py | ||
| simpleroute.py | ||
| sort_db.py | ||
| sp6_bitstream_analyzer.py | ||
| tcl-reformat.sh | ||
| test_fasm2frames.py | ||
| tileconnloops.py | ||
| tileconnwire.py | ||
| tilegrid_report.py | ||
| top_generate.mk | ||
| top_generate.sh | ||
| update_parts.py | ||
| update_parts.tcl | ||
| update_resources.py | ||
| update_resources.tcl | ||
| utils.tcl | ||
| verify_tile_connections.py | ||
| vivado.sh | ||
| vtemplate | ||
| write_timing_info.tcl | ||
| xjson.py | ||
| xyaml.py | ||