Karol Gugala c21b822cfb fuzzers: 074: add zynq7_ignored_wires ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>		2019-01-02 07:01:36 +01:00
..
Makefile	Don't copy tilegrid.json anymore	2018-10-25 19:53:33 -07:00
analyze_errors.py	Add option to output ignored wires and add ignored wires for kintex7.	2018-11-06 08:32:18 -08:00
artix7_ignored_wires.txt	Make ignored wires database specific and have travis be aware of python.	2018-09-27 09:26:02 -07:00
cleanup_site_pins.py	Move xjson / xyaml to utils instead of prjxray.	2018-12-17 17:03:19 -08:00
create_node_tree.py	Move xjson / xyaml to utils instead of prjxray.	2018-12-17 17:03:19 -08:00
generate.sh	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
generate.tcl	tcl: reformat existing code	2018-12-05 16:52:56 -08:00
generate_after_dump.sh	Make 005-tilegrid emit entire part, and have 074-dump_all not overwrite 005-tilegrid.	2018-10-24 07:10:16 -07:00
generate_grid.py	Move xjson / xyaml to utils instead of prjxray.	2018-12-17 17:03:19 -08:00
generate_ignore_list.py	Run make format.	2018-09-27 08:53:39 -07:00
kintex7_ignored_wires.txt	Add option to output ignored wires and add ignored wires for kintex7.	2018-11-06 08:32:18 -08:00
reduce_site_types.py	missing json import	2018-12-23 21:10:22 -08:00
reduce_tile_types.py	Move xjson / xyaml to utils instead of prjxray.	2018-12-17 17:03:19 -08:00
zynq7_ignored_wires.txt	fuzzers: 074: add zynq7_ignored_wires	2019-01-02 07:01:36 +01:00