mirror of https://github.com/openXC7/prjxray.git
Add option to output ignored wires and add ignored wires for kintex7.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
6de8155657
commit
b39e39315d
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@ -1,40 +1,70 @@
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import json
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with open('output/error_nodes.json') as f:
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flat_error_nodes = json.load(f)
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import argparse
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error_nodes = {}
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for node, raw_node, generated_nodes in flat_error_nodes:
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if node not in error_nodes:
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error_nodes[node] = {
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'raw_node': set(raw_node),
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'generated_nodes': set(),
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}
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assert error_nodes[node]['raw_node'] == set(raw_node)
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error_nodes[node]['generated_nodes'].add(tuple(sorted(generated_nodes)))
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def main():
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parser = argparse.ArgumentParser(description="")
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for node, error in error_nodes.items():
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combined_generated_nodes = set()
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for generated_node in error['generated_nodes']:
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combined_generated_nodes |= set(generated_node)
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parser.add_argument('--error_nodes', default='output/error_nodes.json')
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parser.add_argument('--output_ignore_list', action='store_true')
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assert error['raw_node'] == combined_generated_nodes, (node, error)
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args = parser.parse_args()
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good_node = max(error['generated_nodes'], key=lambda x: len(x))
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bad_nodes = error['generated_nodes'] - set((good_node, ))
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with open(args.error_nodes) as f:
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flat_error_nodes = json.load(f)
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if max(len(generated_node) for generated_node in bad_nodes) > 1:
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assert False, node
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else:
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not_pcie = False
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for generated_node in bad_nodes:
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for wire in generated_node:
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if not wire.startswith('PCIE'):
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not_pcie = True
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if not_pcie:
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#print(node, good_node, map(tuple, bad_nodes))
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print(repr((node, tuple(map(tuple, bad_nodes)))))
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pass
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error_nodes = {}
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for node, raw_node, generated_nodes in flat_error_nodes:
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if node not in error_nodes:
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error_nodes[node] = {
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'raw_node': set(raw_node),
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'generated_nodes': set(),
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}
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assert error_nodes[node]['raw_node'] == set(raw_node)
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error_nodes[node]['generated_nodes'].add(
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tuple(sorted(generated_nodes)))
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ignored_wires = set()
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for node, error in error_nodes.items():
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combined_generated_nodes = set()
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for generated_node in error['generated_nodes']:
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combined_generated_nodes |= set(generated_node)
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# Make sure there are not extra wires in nodes.
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assert error['raw_node'] == combined_generated_nodes, (node, error)
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good_node = max(error['generated_nodes'], key=lambda x: len(x))
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bad_nodes = error['generated_nodes'] - set((good_node, ))
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if args.output_ignore_list:
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for generated_node in bad_nodes:
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for wire in generated_node:
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ignored_wires.add(wire)
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continue
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if max(len(generated_node) for generated_node in bad_nodes) > 1:
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assert False, node
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else:
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#print(repr((node, map(tuple, bad_nodes))))
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pass
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not_pcie = False
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for generated_node in bad_nodes:
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for wire in generated_node:
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if not wire.startswith('PCIE'):
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not_pcie = True
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if not_pcie:
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#print(node, good_node, map(tuple, bad_nodes))
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print(repr((node, tuple(map(tuple, bad_nodes)))))
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pass
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else:
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#print(repr((node, map(tuple, bad_nodes))))
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pass
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if args.output_ignore_list:
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for wire in ignored_wires:
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print(wire)
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if __name__ == '__main__':
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main()
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@ -0,0 +1,132 @@
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LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_BOT1
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RIOI_TBYTESRC_X43Y43/RIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y31/RIOI_I2GCLK_TOP1
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CMT_TOP_R_UPPER_B_X8Y135/CMT_PHASER_UP_DQS_TO_PHASER_D
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LIOI3_X0Y45/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_BOT1
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RIOI_TBYTESRC_X43Y57/RIOI_I2GCLK_BOT1
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CMT_TOP_R_LOWER_T_X8Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A
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LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_BOT1
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RIOI_TBYTESRC_X43Y93/RIOI_I2GCLK_TOP1
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LIOI3_X0Y59/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_TOP1
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LIOI3_X0Y179/LIOI_I2GCLK_TOP1
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RIOI_X43Y71/RIOI_I2GCLK_BOT1
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LIOI3_X0Y9/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_BOT1
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CMT_TOP_L_UPPER_B_X108Y83/CMT_PHASER_UP_DQS_TO_PHASER_D
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LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_TOP1
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LIOI3_X0Y79/LIOI_I2GCLK_TOP1
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LIOI3_X0Y191/LIOI_I2GCLK_TOP1
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LIOI3_X0Y195/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_TOP1
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RIOI_X43Y9/RIOI_I2GCLK_BOT1
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RIOI_X43Y83/RIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_TOP1
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RIOI_X43Y17/RIOI_I2GCLK_TOP1
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LIOI3_X0Y17/LIOI_I2GCLK_TOP1
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RIOI_X43Y41/RIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_BOT1
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LIOI3_X0Y159/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y81/LIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y19/RIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y43/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_BOT1
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RIOI_TBYTESRC_X43Y69/RIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_TOP1
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RIOI_X43Y33/RIOI_I2GCLK_BOT1
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RIOI_TBYTETERM_X43Y13/RIOI_I2GCLK_BOT1
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CMT_TOP_R_UPPER_B_X8Y31/CMT_PHASER_UP_DQS_TO_PHASER_D
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LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_BOT1
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RIOI_X43Y95/RIOI_I2GCLK_BOT1
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LIOI3_X0Y21/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_BOT1
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LIOI3_X0Y83/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y181/LIOI_I2GCLK_BOT1
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RIOI_X43Y59/RIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_TOP1
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LIOI3_X0Y145/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y57/LIOI_I2GCLK_TOP1
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LIOI3_X0Y167/LIOI_I2GCLK_TOP1
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LIOI3_X0Y105/LIOI_I2GCLK_TOP1
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LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y37/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y93/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y157/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y131/LIOI_I2GCLK_TOP1
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LIOI3_X0Y171/LIOI_I2GCLK_BOT1
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RIOI_TBYTESRC_X43Y19/RIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y81/RIOI_I2GCLK_TOP1
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LIOI3_X0Y29/LIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_TOP1
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CMT_TOP_L_LOWER_T_X108Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A
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RIOI_TBYTESRC_X43Y57/RIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y43/RIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y193/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_TOP1
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RIOI_TBYTETERM_X43Y37/RIOI_I2GCLK_TOP1
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LIOI3_X0Y33/LIOI_I2GCLK_BOT1
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RIOI_X43Y45/RIOI_I2GCLK_BOT1
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RIOI_X43Y55/RIOI_I2GCLK_TOP1
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LIOI3_X0Y71/LIOI_I2GCLK_BOT1
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RIOI_TBYTETERM_X43Y87/RIOI_I2GCLK_BOT1
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CMT_TOP_L_LOWER_T_X108Y18/CMT_PHASER_DOWN_DQS_TO_PHASER_A
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RIOI_TBYTESRC_X43Y81/RIOI_I2GCLK_BOT1
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CMT_TOP_R_LOWER_T_X8Y122/CMT_PHASER_DOWN_DQS_TO_PHASER_A
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LIOI3_X0Y91/LIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y7/RIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y13/LIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y7/RIOI_I2GCLK_TOP1
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LIOI3_X0Y183/LIOI_I2GCLK_BOT1
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RIOI_X43Y67/RIOI_I2GCLK_TOP1
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LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y87/LIOI_I2GCLK_TOP1
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LIOI3_X0Y109/LIOI_I2GCLK_BOT1
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RIOI_X43Y21/RIOI_I2GCLK_BOT1
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LIOI3_X0Y67/LIOI_I2GCLK_TOP1
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LIOI3_X0Y121/LIOI_I2GCLK_BOT1
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RIOI_X43Y5/RIOI_I2GCLK_TOP1
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CMT_TOP_R_LOWER_T_X8Y174/CMT_PHASER_DOWN_DQS_TO_PHASER_A
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RIOI_TBYTESRC_X43Y93/RIOI_I2GCLK_BOT1
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LIOI3_X0Y129/LIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y107/LIOI_I2GCLK_TOP1
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LIOI3_TBYTETERM_X0Y63/LIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y69/RIOI_I2GCLK_TOP1
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LIOI3_X0Y117/LIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y119/LIOI_I2GCLK_TOP1
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RIOI_X43Y91/RIOI_I2GCLK_TOP1
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LIOI3_TBYTETERM_X0Y113/LIOI_I2GCLK_BOT1
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CMT_TOP_R_UPPER_B_X8Y187/CMT_PHASER_UP_DQS_TO_PHASER_D
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RIOI_X43Y29/RIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y31/LIOI_I2GCLK_TOP1
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LIOI3_X0Y55/LIOI_I2GCLK_TOP1
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RIOI_TBYTETERM_X43Y87/RIOI_I2GCLK_TOP1
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RIOI_TBYTETERM_X43Y63/RIOI_I2GCLK_TOP1
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LIOI3_TBYTESRC_X0Y69/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y143/LIOI_I2GCLK_BOT1
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LIOI3_X0Y141/LIOI_I2GCLK_TOP1
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LIOI3_TBYTETERM_X0Y163/LIOI_I2GCLK_TOP1
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RIOI_X43Y79/RIOI_I2GCLK_TOP1
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RIOI_TBYTETERM_X43Y37/RIOI_I2GCLK_BOT1
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CMT_TOP_R_LOWER_T_X8Y70/CMT_PHASER_DOWN_DQS_TO_PHASER_A
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RIOI_TBYTETERM_X43Y63/RIOI_I2GCLK_BOT1
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LIOI3_X0Y41/LIOI_I2GCLK_TOP1
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LIOI3_X0Y155/LIOI_I2GCLK_TOP1
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LIOI3_X0Y95/LIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_TOP1
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RIOI_TBYTETERM_X43Y13/RIOI_I2GCLK_TOP1
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RIOI_TBYTESRC_X43Y31/RIOI_I2GCLK_BOT1
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LIOI3_TBYTESRC_X0Y7/LIOI_I2GCLK_TOP1
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CMT_TOP_R_UPPER_B_X8Y83/CMT_PHASER_UP_DQS_TO_PHASER_D
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LIOI3_TBYTESRC_X0Y169/LIOI_I2GCLK_BOT1
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LIOI3_X0Y133/LIOI_I2GCLK_BOT1
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CMT_TOP_L_UPPER_B_X108Y31/CMT_PHASER_UP_DQS_TO_PHASER_D
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LIOI3_TBYTETERM_X0Y137/LIOI_I2GCLK_BOT1
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LIOI3_TBYTETERM_X0Y187/LIOI_I2GCLK_TOP1
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LIOI3_X0Y5/LIOI_I2GCLK_TOP1
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