mirror of https://github.com/openXC7/prjxray.git
1ebe6937e0
The earlier skip blamed a 'Vivado 2020.1 BEL-slot' difference; on close
investigation the real failure was generate.py:79 `assert bels == bels_tcl`
in the my_ram_N branch. The two ROI definitions disagree on X extent:
util.get_roi() (XRAY_ROI_GRID_*) yields SLICEM at SLICE X2..X12, but the
Vivado dump pblock built from $XRAY_ROI is X0..X11 — so the whole
SLICE_X12Y* column top.py LOC's primitives into falls outside the dumped
pblock and shows up as None in design.csv, tripping the assert.
The sibling RAM path already tolerated this via 'if ram != has_bel_tcl:
continue' (line ~137); mirror the same graceful skip in the SRL/LUT path.
For other families bels always == bels_tcl, so the change is a no-op.
Verified end-to-end on xc7vx485tffg1761-2: produces valid LUTRAM segdata
(ALUT/BLUT/CLUT/DLUT.{RAM,SRL,SMALL} + WA7USED/WA8USED/WEMUX.CE), pushes
into segbits_clblm_l/r (clblm coverage 95% -> ~100% vs kintex7).
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
|
||
|---|---|---|
| .. | ||
| minitest | ||
| Makefile | ||
| README.md | ||
| generate.py | ||
| generate.sh | ||
| generate.tcl | ||
| top.py | ||
README.md
clb-ram Fuzzer
| Primitive | RAM | SMALL | SRL |
|---|---|---|---|
| LUT6 | |||
| SRL16E | X | X | |
| SRLC32E | X | ||
| RAM32X1S | X | X | |
| RAM64X1S | X | ||
| RAM32M | X | X | |
| RAM32X1D | X | X | |
| RAM64M | X | ||
| RAM64X1D | X | ||
| RAM128X1D | X | ||
| RAM256X1S | X | ||
| RAM128X1S | X |
NLUT.RAM
Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.
NLUT.SMALL
Seems to be set on smaller primitives.
NLUT.SRL
Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E
WA7USED
Set to 1 to propagate CLB's CX input to WA7
WA8USED
Set to 1 to propagate CLB's BX input to WA8
WEMUX.CE
| WEMUX.CE | CLB RAM write enable |
|---|---|
| 0 | CLB WE input |
| 1 | CLB CE input |