mirror of https://github.com/openXC7/prjxray.git
39f5de415d
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families. Family registration: - settings/virtex7.sh, settings/virtex7/devices.yaml - Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets - utils/update_parts.py, update_resources.py: virtex7 choice - CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README Architecture adaptations for the HP-bank-only VX part (verified non-breaking): - update_resources.tcl: fall back to HP banks when no HR banks exist - XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised across the fuzzer generate.tcl files - fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7; GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads) - 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2; ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles; per-specimen retry for transient FlexLM SIGSEGV under concurrency - per-family Vivado version gate (virtex7 -> v2020.1.1) - XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region General fixes: - tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the larger Virtex-7 bitstream) - utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable install doesn't expose the repo-root utils/ package) Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com> |
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|---|---|---|
| .. | ||
| minitest | ||
| Makefile | ||
| README.md | ||
| bits.dbf | ||
| generate.py | ||
| generate.sh | ||
| generate.tcl | ||
| prims.py | ||
| top.py | ||
README.md
clb-ffconfig Fuzzer
Documents FF configuration.
Note Vivado GUI is misleading in some cases where it shows configuration per FF, but its actually per SLICE
Primitive pin map
| Element | CE | CK | D | SR | Q |
|---|---|---|---|---|---|
| FDRE | CE | C | D | R | Q |
| FDPE | CE | C | D | PRE | Q |
| FDSE | CE | C | D | S | Q |
| FDCE | CE | C | D | CLR | Q |
| LDPE | GE | G | D | PRE | Q |
| LDCE | GE | G | D | CLR | Q |
Primitive bit map
| Prim | FFSYNC | LATCH | ZRST |
|---|---|---|---|
| FDPE | |||
| FDSE | X | ||
| FDRE | X | X | |
| FDCE | X | ||
| LDCE | X | X | |
| LDPE | X |
FFSYNC
Configures whether a storage element is synchronous or asynchronous.
Scope: entire site (not individual FFs)
| FFSYNC | Reset | Applicable prims |
|---|---|---|
| 0 | Asynchronous | FDPE, FDCE, LDCE, LDPE |
| 1 | Synchronous | FDSE, FDRE |
LATCH
Configures latch vs FF behavior for the CLB
| LATCH | Description | Primitives |
|---|---|---|
| 0 | All storage elements in the CLB are FF's | FDPE, FDSE, FDRE, FDCE |
| 1 | LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used | LDCE, LDPE |
N*FF.ZRST
Configures stored value when reset is asserted
| Prim | ZRST | On reset |
|---|---|---|
| FDRE, FDCE, and LDCE | 0 | 1 |
| FDRE, FDCE, and LDCE | 1 | 0 |
| FDPE, FDSE, and LDPE | 0 | 0 |
| FDPE, FDSE, and LDPE | 1 | 1 |
N*FF.ZINI
Sets GSR FF or latch value
| LATCH | ZINI | Set to |
|---|---|---|
| FF | 0 | 1 |
| FF | 1 | 0 |
| LATCH | 0 | 0 |
| LATCH | 1 | 1 |
CEUSEDMUX
Configures ability to drive clock enable (CE) or always enable clock
| CEUSEDMUX | Description |
|---|---|
| 0 | always on (CE=1) |
| 1 | controlled (CE=mywire) |
SRUSEDMUX
Configures ability to reset FF after GSR
| SRUSEDMUX | Description |
|---|---|
| 0 | never reset (R=0) |
| 1 | controlled (R=mywire) |
TODO: how used when SR?
CLKINV
Configures whether to invert the clock going into a slice.
Scope: entire site (not individual FFs)
| LATCH | CLKINV | Description |
|---|---|---|
| FF | 0 | normal clock |
| FF | 1 | invert clock |
| LATCH | 0 | invert clock |
| LATCH | 1 | normal clock |